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ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 1 ? 2009?2011 xilinx, inc. xilinx, the xilinx logo, virtex, zynq, artix, kintex, spartan, ise, and other designated brands includ ed herein are trademarks of xilinx in the united states and other countries. all other trademarks are the property of their respective owners. spartan-6 fpga electrical characteristics spartan?-6 lx fpgas are available in -3, -3n, -2, and -1l speed grades, with -3 having the highest performance. spartan-6 lxt fpgas are available in -3, -3n, and -2 speed grades, with -3 having the highest performance. spartan-6 fpga dc and ac characteristics are specified for both commercial and industrial grades. except the operating temperature range or unless otherwise noted, all the dc and ac electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -2 speed grade industrial device are the same as for a -2 speed grade commercial device). however, only selected speed grades and/or devices might be available in the industrial range. the spartan-6 fpga -3n speed grade designates devices that do not support mcb functionality. all supply voltage and junction temperature specifications are representative of worst-case conditions. the parameters included are common to popular designs and typical applications. this spartan-6 fpga data sheet, part of an overall set of documentation on the spartan-6 family of fpgas, is available on the xilinx website. all specifications are subject to change without notice. spartan-6 fpga dc characteristics 76 spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 preliminary product specification ta bl e 1 : absolute maximum ratings (1) symbol description units v ccint internal supply voltage rela tive to gnd ?0.5 to 1.32 v v ccaux auxiliary supply voltage relative to gnd ?0.5 to 3.75 v v cco output drivers supply voltage relative to gnd ?0.5 to 3.75 v v batt key memory battery backup supply (xc6sl x75, xc6slx75t, xc6slx100, xc6slx100t, xc6slx150, and xc6slx150t only) ?0.5 to 4.05 v v fs external voltage supply for efuse programming (xc6slx75, xc6slx75t, xc6slx100, xc6slx100t, xc6slx150, and xc6slx150t only) (2) ?0.5 to 3.75 v v ref input reference voltage ?0.5 to 3.75 v v in and v ts (3) i/o input voltage or voltage applied to 3-state output, relative to gnd (4) all user and dedicated i/os commercial dc ?0.60 to 4.10 v 20% overshoot duration ?0.75 to 4.25 v 8% overshoot duration (5) ?0.75 to 4.40 v industrial dc ?0.60 to 3.95 v 20% overshoot duration ?0.75 to 4.15 v 4% overshoot duration (5) ?0.75 to 4.40 v restricted to maximum of 100 user i/os commercial 20% overshoot duration ?0.75 to 4.35 v 15% overshoot duration (5) ?0.75 to 4.40 v 10% overshoot duration ?0.75 to 4.45 v industrial 20% overshoot duration ?0.75 to 4.25 v 10% overshoot duration ?0.75 to 4.35 v 8% overshoot duration (5) ?0.75 to 4.40 v
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 2 t stg storage temperature (ambient) ?65 to 150 c t sol maximum soldering temperature (6) (tqg144, cpg196, cs g225, csg324, csg484, and ftg256) +260 c maximum soldering temperature (6) (pb-free packages: fgg484, fgg676, and fgg900) +250 c maximum soldering temperature (6) (pb packages: ft256, fg 484, fg676, and fg900) +220 c t j maximum junction temperature (6) ? 125 c notes: 1. stresses beyond those listed under absolute maximum ratings mi ght cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions bey ond those listed under operating conditions is not impli ed. exposure to absolute maximum ratings conditions for extended perio ds of time might affect device reliability. 2. when programming efuse, v fs ? v ccaux . requires up to 40 ma current. for read mode, v fs can be between gnd and 3.45 v. 3. i/o absolute maximum limit applied to dc and ac signals. overshoot duration is the percentage of a data period that the i/o i s stressed beyond 3.45v. 4. for i/o operation, refer to the spartan-6 fpga selectio resources user guide. 5. maximum percent overshoot duration to meet 4.40v maximum. 6. for soldering guidelines and thermal considerations, see spartan-6 fpga packaging and pinout specification . ta bl e 2 : recommended operating conditions (1) symbol description temperature range speed grade memory controller block (2) performance min typ max units v ccint internal supply voltage relative to gnd, t j =0 ? c to +85 ? c commercial -3, -3n, -2 standard 1.14 1.2 1.26 v -3, -2 extended 1.2 1.23 1.26 v -1l standard 0.95 1.0 1.05 v internal supply voltage relative to gnd, t j =?40 ? c to +100 ? c industrial -3, -3n, -2 standard 1.14 1.2 1.26 v -3, -2 extended 1.2 1.23 1.26 v -1l standard 0.95 1.0 1.05 v v ccaux (3)(4) auxiliary supply voltage relative to gnd when v ccaux =2.5v, t j =0 ? c to +85 ? c commercial -3, -3n, -2, -1l n/a 2.375 2.5 2.625 v auxiliary supply voltage relative to gnd when v ccaux =2.5v, t j =?40 ? c to +100 ? c industrial -3, -3n, -2, -1l n/a auxiliary supply voltage relative to gnd when v ccaux =3.3v, t j =0 ? c to +85 ? c commercial -3, -3n, -2, -1l (5) n/a 3.15 3.3 3.45 v auxiliary supply voltage relative to gnd when v ccaux =3.3v, t j =?40 ? c to +100 ? c industrial -3, -3n, -2, -1l (5) n/a v cco (6)(7)(8) output supply voltage relative to gnd, t j =0 ? c to +85 ? c commercial -3, -3n, -2, -1l n/a 1.1 ? 3.45 v output supply voltage relative to gnd, t j =?40 ? c to +100 ? c industrial -3, -3n, -2, -1l n/a v in input voltage relative to gnd, t j =0 ? c to +85 ? c commercial -3, -3n, -2, -1l n/a ?0.5 ? 4.0 v input voltage relative to gnd, t j = ?40 ? c to +100 ? c industrial -3, -3n, -2, -1l n/a ?0.5 ? 3.95 v input voltage relative to gnd, pci i/o standard, t j =0 ? c to +85 ? c commercial -3, -3n, -2, -1l (9) n/a ?0.5 ? v cco + 0.5 v input voltage relative to gnd, pci i/o standard, t j =?40 ? c to +100 ? c industrial -3, -3n, -2, -1l (9) n/a ?0.5 ? v cco + 0.5 v ta bl e 1 : absolute maximum ratings (1) (cont?d) symbol description units
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 3 i in (10) maximum current through pin using pci i/o standard when forward biasing the clamp diode. commercial -3, -3n, -2, -1l (9) n/a ??10ma industrial -3, -3n,-2, -1l (9) n/a ??10ma v batt (11) battery voltage relative to gnd, t j =0 ? c to +85 ? c (xc6slx75, xc6slx75t, xc6slx100, xc6slx100t, xc6slx150, and xc6slx150t only) commercial -3, -3n, -2, -1l n/a 1.0 ? 3.6 v battery voltage relative to gnd, t j =?40 ? c to +100 ? c (xc6slx75, xc6slx75t, xc6slx100, xc6slx100t, xc6slx150, and xc6slx150t only) industrial -3, -3n, -2, -1l n/a notes: 1. all voltages are relative to ground. 2. see interface performances for memory interfaces in ta bl e 2 5 . the standard v ccint voltage range applies to designs not using an mcb, or to devices that do not support mcb functionality including the lx4 de vice, the tqg144 and cpg196 packages, and the -3n speed grade . 3. recommended maximum voltage droop for v ccaux is 10 mv/ms. 4. during configuration, if v cco_2 is 1.8v, then v ccaux must be 2.5v. 5. the -1l devices require v ccaux = 2.5v when using the lvds_25, lvds_33, blvds _25, lvpecl_25, rsds_25, rsds_33, ppds_25, and ppds_33 i/o standards on inputs. lvpecl_33 is not supported in the -1l devices. 6. configuration data is retained even if v cco drops to 0v. 7. includes v cco of 1.2v, 1.5v, 1.8v, 2.5v, and 3.3v. 8. for pci systems, the transmitter and receiver should have common supplies for v cco . 9. devices with a -1l speed grade do not support xilinx pci ip. 10. do not exceed a total of 100 ma per bank. 11. v batt is required to maintain the battery backed ram (bbr) aes key when v ccaux is not applied. once v ccaux is applied, v batt can be unconnected. when bbr is not used, xilinx recommends connecting to v ccaux or gnd. however, v batt can be unconnected. ta bl e 3 : efuse programming conditions (1) symbol description min typ max units v fs (2) external voltage supply 3.2 3.3 3.4 v i fs v fs supply current ??40ma v ccaux auxiliary supply voltage relative to gnd 3.2 3.3 3.45 v r fuse (3) external resistor from r fuse pin to gnd 1129 1140 1151 ? v ccint internal supply voltage relative to gnd 1.14 1.2 1.26 v t j temperature range 15?85c notes: 1. these specifications apply during programming of the efuse aes key. programming is only supported through jtag.the aes key is only supported in the following devices: xc6slx75, xc6slx75t, xc6slx100, xc6slx100t, xc6slx150, and xc6slx150t. 2. when programming efuse, v fs must be less than or equal to v ccaux . when not programming or when efu se is not used, xilinx recommends connecting v fs to gnd. however, v fs can be between gnd and 3.45 v. 3. an r fuse resistor is required when programming the efuse aes key. when not programming or when efuse is not used, xilinx recommends connecting the r fuse pin to v ccaux or gnd. however, r fuse can be unconnected. ta bl e 2 : recommended operating conditions (1) (cont?d) symbol description temperature range speed grade memory controller block (2) performance min typ max units
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 4 ta bl e 4 : dc characteristics over recommended operating conditions symbol description min typ max units v drint data retention v ccint voltage (below which configur ation data might be lost) 0.8 ? ? v v draux data retention v ccaux voltage (below which configuration data might be lost) 2.0 ? ? v i ref v ref leakage current per pin ?10 ? 10 a i l input or output leakage current per pin (sample-tested) ?10 ? 10 a i hs leakage current on pins during hot socketing with fpga unpowered all pins except program_b, done, and jtag pins when hswapen = 1 ?20 ? 20 a program_b, done, and jtag pins, or other pins when hswapen = 0 i hs + i rpu a c in die input capacitance at the pad ? ? 10 pf i rpu pad pull-up (when selected) @ v in =0v, v cco =3.3v or v ccaux = 3.3v 200 ? 500 a pad pull-up (when selected) @ v in =0v, v cco =2.5v or v ccaux = 2.5v 120 ? 350 a pad pull-up (when selected) @ v in =0v, v cco = 1.8v 60 ? 200 a pad pull-up (when selected) @ v in =0v, v cco = 1.5v 40 ? 150 a pad pull-up (when selected) @ v in =0v, v cco = 1.2v 12 ? 100 a i rpd pad pull-down (when selected) @ v in =v cco , v ccaux = 3.3v 200 ? 550 a pad pull-down (when selected) @ v in =v cco , v ccaux = 2.5v 140 ? 400 a i batt (1) battery supply current ? ? 150 na r dt (2) resistance of optional input differential termination circuit, v ccaux =3.3v ? 100 ? ? r in_term (4) thevenin equivalent resistance of programmable input termination (untuned_split_25) 23 25 55 ? thevenin equivalent resistance of programmable input termination (untuned_split_50) 39 50 72 ? thevenin equivalent resistance of programmable input termination (untuned_split_75) 56 75 109 ? notes: 1. maximum value specified for worst case process at 25c. xc 6slx75, xc6slx75t, xc6slx100, xc6slx100t, xc6slx150, and xc6slx150t only. 2. refer to ibis models for r dt variation and for values at v ccaux = 2.5v. ibis values for r dt are valid for all temperature ranges. 3. v cco2 is not required for data retention. the minimum v cco2 for power-on reset and configuration is 1.65v. 4. termination resistance to a v cco /2 level.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 5 quiescent current typical values for quiescent supply current are specified at nominal voltage, 25c junction temperatures (t j ). quiescent supply current is specified by speed gr ade for spartan-6 devices. xilinx recommen ds analyzing static power consumption using the xpower? estimator (xpe) tool (download at http://www.xilinx.com/power ) for conditions other than those specified in ta bl e 5 . ta bl e 5 : typical quiescent supply current symbol description device speed grade units -3 -3n -2 -1l i ccintq quiescent v ccint supply current xc6slx4 4.0 4.0 4.0 2.4 ma xc6slx9 4.0 4.0 4.0 2.4 ma xc6slx16 6.0 6.0 6.0 4.0 ma xc6slx25 11.0 11.0 11.0 6.6 ma xc6slx25t 11.0 11.0 11.0 n/a ma xc6slx45 15.0 15.0 15.0 9.0 ma xc6slx45t 15.0 15.0 15.0 n/a ma xc6slx75 29.0 29.0 29.0 17.4 ma xc6slx75t 29.0 29.0 29.0 n/a ma xc6slx100 36.0 36.0 36.0 21.6 ma xc6slx100t 36.0 36.0 36.0 n/a ma xc6slx150 51.0 51.0 51.0 31.0 ma xc6slx150t 51.0 51.0 51.0 n/a ma i ccoq quiescent v cco supply current xc6slx4 1.0 1.0 1.0 1.0 ma xc6slx9 1.0 1.0 1.0 1.0 ma xc6slx16 2.0 2.0 2.0 2.0 ma xc6slx25 2.0 2.0 2.0 2.0 ma xc6slx25t 2.0 2.0 2.0 n/a ma xc6slx45 3.0 3.0 3.0 3.0 ma xc6slx45t 3.0 3.0 3.0 n/a ma xc6slx75 4.0 4.0 4.0 4.0 ma xc6slx75t 4.0 4.0 4.0 n/a ma xc6slx100 5.0 5.0 5.0 5.0 ma xc6slx100t 5.0 5.0 5.0 n/a ma xc6slx150 7.0 7.0 7.0 7.0 ma xc6slx150t 7.0 7.0 7.0 n/a ma
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 6 i ccauxq quiescent v ccaux supply current xc6slx4 2.5 2.5 2.5 2.5 ma xc6slx9 2.5 2.5 2.5 2.5 ma xc6slx16 3.0 3.0 3.0 3.0 ma xc6slx25 4.0 4.0 4.0 4.0 ma xc6slx25t 4.0 4.0 4.0 n/a ma xc6slx45 5.0 5.0 5.0 5.0 ma xc6slx45t 5.0 5.0 5.0 n/a ma xc6slx75 7.0 7.0 7.0 7.0 ma xc6slx75t 7.0 7.0 7.0 n/a ma xc6slx100 9.0 9.0 9.0 9.0 ma xc6slx100t 9.0 9.0 9.0 n/a ma xc6slx150 12.0 12.0 12.0 12.0 ma xc6slx150t 12.0 12.0 12.0 n/a ma notes: 1. typical values are specified at nominal voltage, 25c junction temperatures (t j ). industrial (i) grade devices have the same typical values as commercial (c) grade devices at 25c, but higher values at 100c. use the xpe tool to calculate 100c values. nominal v ccint is 1.20v; use the xpe tool to calculate 1.23v values for the nominal v ccint of the extended mcb performance range. 2. typical values are for blank configured devices with no output current loads, no acti ve input pull-up resi stors, all i/o pins are 3-state and floating. 3. if differential signaling is used, more accurate quiescent cu rrent estimates can be obtained by using the xpower estimator (x pe) or xpower analyzer (xpa) tools. ta bl e 6 : power supply ramp time symbol description speed grade ramp time units v ccintr internal supply voltage ramp time -3, -3n, -2 0.20 to 50.0 ms -1l 0.20 to 40.0 ms v cco2 (1) output drivers bank 2 supply voltage ramp time all 0.20 to 50.0 ms v ccauxr auxiliary supply voltage ramp time all 0.20 to 50.0 ms notes: 1. the minimum v cco2 for power-on reset and configuration is 1.65v 2. spartan-6 fpgas require a certain amount of supply current duri ng power-on to insure proper device initialization. the actual current consumed depends on the power-on ramp rate of the power supply. use the xpow er estimator (xpe) or xpower analyzer (xpa) tools to estimat e current drain on these supplies. spartan-6 device s do not have a required power-on sequence. ta bl e 5 : typical quiescent supply current (cont?d) symbol description device speed grade units -3 -3n -2 -1l
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 7 selectio? interface dc input and output levels ta bl e 7 : recommended operating conditions for user i/os using single-ended standards i/o standard v cco for drivers (1) v ref for inputs v, min v, nom v, max v, min v, nom v, max lvttl 3.0 3.3 3.45 v ref is not used for these i/o standards lvcmos33 3.0 3.3 3.45 lvcmos25 2.3 2.5 2.7 lvcmos18 1.65 1.8 1.95 lvcmos18_jedec 1.65 1.8 1.95 lvcmos15 1.4 1.5 1.6 lvcmos15_jedec 1.4 1.5 1.6 lvcmos12 1.1 1.2 1.3 lvcmos12_jedec 1.1 1.2 1.3 pci33_3 (2) 3.0 3.3 3.45 pci66_3 (2) 3.0 3.3 3.45 i2c 2.7 3.0 3.45 smbus 2.7 3.0 3.45 sdio 3.0 3.3 3.45 mobile_ddr 1.7 1.8 1.9 hstl_i 1.4 1.5 1.6 0.68 0.75 0.9 hstl_ii 1.4 1.5 1.6 0.68 0.75 0.9 hstl_iii 1.4 1.5 1.6 ? 0.9 ? hstl_i_18 1.7 1.8 1.9 0.8 0.9 1.1 hstl_ii_18 1.7 1.8 1.9 ? 0.9 ? hstl_iii_18 1.7 1.8 1.9 ? 1.1 ? sstl3_i 3.0 3.3 3.45 1.3 1.5 1.7 sstl3_ii 3.0 3.3 3.45 1.3 1.5 1.7 sstl2_i 2.3 2.5 2.7 1.13 1.25 1.38 sstl2_ii 2.3 2.5 2.7 1.13 1.25 1.38 sstl18_i 1.7 1.8 1.9 0.833 0.9 0.969 sstl18_ii 1.7 1.8 1.9 0.833 0.9 0.969 sstl15_ii 1.425 1.5 1.575 0.69 0.75 0.81 notes: 1. v cco range required when using i/o standard for an output. also required for pci33_3, lvcmos18_jedec, lvcmos15_jedec, and lvcmos12_jedec inputs, and for lvcmos25 inputs when v ccaux =3.3v. 2. for pci systems, the transmitter and receiver should have common supplies for v cco .
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 8 ta bl e 8 : recommended operating conditions for user i /os using differential signal standards i/o standard v cco for drivers v, min v, nom v, max lvds_33 3.0 3.3 3.45 lvds_25 2.25 2.5 2.75 blvds_25 2.25 2.5 2.75 mini_lvds_33 3.0 3.3 3.45 mini_lvds_25 2.25 2.5 2.75 lvpecl_33 (1) n/a?inputs only lvpecl_25 n/a?inputs only rsds_33 3.0 3.3 3.45 rsds_25 2.25 2.5 2.75 tmds_33 (1) 3.14 3.3 3.45 ppds_33 3.0 3.3 3.45 ppds_25 2.25 2.5 2.75 display_port 2.3 2.5 2.7 diff_mobile_ddr 1.7 1.8 1.9 diff_hstl_i 1.4 1.5 1.6 diff_hstl_ii 1.4 1.5 1.6 diff_hstl_iii 1.4 1.5 1.6 diff_hstl_i_18 1.7 1.8 1.9 diff_hstl_ii_18 1.7 1.8 1.9 diff_hstl_iii_18 1.7 1.8 1.9 diff_sstl3_i 3.0 3.3 3.45 diff_sstl3_ii 3.0 3.3 3.45 diff_sstl2_i 2.3 2.5 2.7 diff_sstl2_ii 2.3 2.5 2.7 diff_sstl18_i 1.7 1.8 1.9 diff_sstl18_ii 1.7 1.8 1.9 diff_sstl15_ii 1. 425 1.5 1.575 notes: 1. lvpecl_33 and tmds_33 inputs require v ccaux = 3.3v nominal.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 9 in ta bl e 9 and ta bl e 1 0 , values for v il and v ih are recommended input voltages. values for i ol and i oh are guaranteed over the recommended operating conditions at the v ol and v oh test points. only selected standards are tested. these are chosen to ensure that all standards meet their specifications. the selected standards are tested at a minimum v cco with the respective v ol and v oh voltage levels shown. other standards are sample tested. ta bl e 9 : single-ended i/o standard dc input and output levels i/o standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma lvttl ?0.5 0.8 2.0 4.1 0.4 2.4 note(2) note(2) lvcmos33 ?0.5 0.8 2.0 4.1 0.4 v cco ? 0.4 note(2) note(2) lvcmos25 ?0.5 0.7 1.7 4.1 0.4 v cco ? 0.4 note(2) note(2) lvcmos18 ?0.5 0.38 0.8 4.1 0.45 v cco ? 0.45 note(2) note(2) lvcmos18 (-1l) ?0.5 0.33 0.71 4.1 0.45 v cco ? 0.45 note(2) note(2) lvcmos18_jedec ?0.5 35% v cco 65% v cco 4.1 0.45 v cco ? 0.45 note(2) note(2) lvcmos15 ?0.5 0.38 0.8 4.1 25% v cco 75% v cco note(3) note(3) lvcmos15 (-1l) ?0.5 0.33 0.71 4.1 25% v cco 75% v cco note(3) note(3) lvcmos15_jedec ?0.5 35% v cco 65% v cco 4.1 25% v cco 75% v cco note(3) note(3) lvcmos12 ?0.5 0.38 0.8 4.1 0.4 v cco ? 0.4 note(4) note(4) lvcmos12 (-1l) ?0.5 0.33 0.71 4.1 0.4 v cco ? 0.4 note(4) note(4) lvcmos12_jedec ?0.5 35% v cco 65% v cco 4.1 0.4 v cco ? 0.4 note(4) note(4) pci33_3 ?0.5 30% v cco 50% v cco v cco + 0.5 10% v cco 90% v cco 1.5 ?0.5 pci66_3 ?0.5 30% v cco 50% v cco v cco + 0.5 10% v cco 90% v cco 1.5 ?0.5 i2c ?0.5 25% v cco 70% v cco 4.1 20% v cco ?3? smbus ?0.5 0.8 2.1 4.1 0.4 ? 4 ? sdio ?0.5 12.5% v cco 75% v cco 4.1 12.5% v cco 75% v cco 0.1 ?0.1 mobile_ddr ?0.5 20% v cco 80% v cco 4.1 10% v cco 90% v cco 0.1 ?0.1 hstl_i ?0.5 v ref ?0.1 v ref + 0.1 4.1 0.4 v cco ?0.4 8 ?8 hstl_ii ?0.5 v ref ?0.1 v ref + 0.1 4.1 0.4 v cco ? 0.4 16 ?16 hstl_iii ?0.5 v ref ?0.1 v ref + 0.1 4.1 0.4 v cco ? 0.4 24 ?8 hstl_i_18 ?0.5 v ref ?0.1 v ref + 0.1 4.1 0.4 v cco ? 0.4 11 ?11 hstl_ii_18 ?0.5 v ref ?0.1 v ref + 0.1 4.1 0.4 v cco ? 0.4 22 ?22 hstl_iii_18 ?0.5 v ref ?0.1 v ref + 0.1 4.1 0.4 v cco ? 0.4 30 ?11 sstl3_i ?0.5 v ref ?0.2 v ref +0.2 4.1 v tt ?0.6 v tt +0.6 8 ?8 sstl3_ii ?0.5 v ref ?0.2 v ref +0.2 4.1 v tt ?0.8 v tt + 0.8 16 ?16 sstl2_i ?0.5 v ref ?0.15 v ref +0.15 4.1 v tt ?0.61 v tt + 0.61 8.1 ?8.1 sstl2_ii ?0.5 v ref ?0.15 v ref +0.15 4.1 v tt ?0.81 v tt + 0.81 16.2 ?16.2 sstl18_i ?0.5 v ref ? 0.125 v ref + 0.125 4.1 v tt ?0.47 v tt + 0.47 6.7 ?6.7 sstl18_ii ?0.5 v ref ? 0.125 v ref + 0.125 4.1 v tt ?0.60 v tt + 0.60 13.4 ?13.4 sstl15_ii ?0.5 v ref ?0.1 v ref +0.1 4.1 v tt ?0.4 v tt + 0.4 13.4 ?13.4 notes: 1. tested according to relevant specifications. 2. using drive strengths of 2, 4, 6, 8, 12, 16, or 24 ma. 3. using drive strengths of 2, 4, 6, 8, 12, or 16 ma. 4. using drive strengths of 2, 4, 6, 8, or 12 ma. 5. for more information, refer to the spartan-6 fpga selectio resources user guide.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 10 ta bl e 1 0 : differential i/o standard dc input and output levels i/o standard v id v icm v od v ocm v oh v ol mv, min mv, max v, min v, max mv, min mv, max v, min v, max v, min v, max lvds_33 (2)(3) 100 600 0.3 2.35 247 454 1.125 1.375 ? ? lvds_25 (2)(3) 100 600 0.3 2.35 247 454 1.125 1.375 ? ? blvds_25 (2)(3) 100 ? 0.3 2.35 240 460 typical 50% v cco ?? mini_lvds_33 200 600 0.3 1.95 300 600 1.0 1.4 ? ? mini_lvds_25 200 600 0.3 1.95 300 600 1.0 1.4 ? ? lvpecl_33 (2)(3) 100 1000 0.3 2.8 (1) inputs only lvpecl_25 (2)(3) 100 1000 0.3 1.95 inputs only rsds_33 (2)(3) 100 ? 0.3 1.5 100 400 1.0 1.4 ? ? rsds_25 (2)(3) 100 ? 0.3 1.5 100 400 1.0 1.4 ? ? tmds_33 150 1200 2.7 3.23 (1) 400 800 v cco ?0.405 v cco ? 0.190 ? ? ppds_33 (2)(3) 100 400 0.2 2.3 100 400 0.5 1.4 ? ? ppds_25 (2)(3) 100 400 0.2 2.3 100 400 0.5 1.4 ? ? display_port 190 1260 0.3 2.35 ? ? typical 50% v cco ?? diff_mobile_ddr 100 ? 0.78 1.02 ? ? ? ? 90% v cco 10% v cco diff_hstl_i 100 ? 0.68 0.9 ? ? ? ? v cco ?0.4 0.4 diff_hstl_ii 100 ? 0.68 0.9 ? ? ? ? v cco ?0.4 0.4 diff_hstl_iii 100 ? 0.68 0.9 ? ? ? ? v cco ?0.4 0.4 diff_hstl_i_18 100 ? 0.8 1.1 ? ? ? ? v cco ?0.4 0.4 diff_hstl_ii_18 100 ? 0.8 1.1 ? ? ? ? v cco ?0.4 0.4 diff_hstl_iii_18 100 ? 0.8 1.1 ? ? ? ? v cco ?0.4 0.4 diff_sstl3_i 100 ? 1.0 1.9 ? ? ? ? v tt +0.6 v tt ?0.6 diff_sstl3_ii 100 ? 1.0 1.9 ? ? ? ? v tt +0.8 v tt ?0.8 diff_sstl2_i 100 ? 1.0 1.5 ? ? ? ? v tt +0.61 v tt ?0.61 diff_sstl2_ii 100 ? 1.0 1.5 ? ? ? ? v tt +0.81 v tt ?0.81 diff_sstl18_i 100 ? 0.7 1.1 ? ? ? ? v tt +0.47 v tt ?0.47 diff_sstl18_ii 100 ? 0.7 1.1 ? ? ? ? v tt +0.6 v tt ?0.6 diff_sstl15_ii 100 ? 0.55 0.95 ? ? ? ? v tt +0.4 v tt ?0.4 notes: 1. lvpecl_33 and tmds_33 maximum v icm is the lower of v (maximum) or v ccaux ?(v id /2) 2. when v ccaux = 3.3v, the dcd can be higher than 5% for v icm < 0.7v when using these i/o standards: lvds_25, lvds_33, blvds_25, lvpecl_25, lvpecl_33, rsds_25, rsds_33, ppds_25, and ppds_33. 3. the -1l devices require v ccaux = 2.5v when using the lvds_25, lvds_33, blvds _25, lvpecl_25, rsds_25, rsds_33, ppds_25, and ppds_33 i/o standards on inputs. lvpecl_33 is not supported in the -1l devices.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 11 efuse read endurance ta bl e 1 1 lists the minimum guaranteed number of read cycle operations for device dna and for the aes efuse key. for more information, see the spartan-6 fpga configuration user guide . gtp transceiver specifications gtp transceivers are available in the spartan-6 lxt family of devices. see ds160 : spartan-6 family overview for more information. gtp transceiver dc characteristics ta bl e 1 1 : efuse read endurance symbol description speed grade units (min) -3 -3n -2 -1l dna_cycles number of dna_port read operations or jtag isc_dna read command operations. unaffected by shift operations. 30,000,000 read cycles aes_cycles number of jtag fuse_key or fuse_cntl read co mmand operations. unaffected by shift operations. 30,000,000 read cycles ta bl e 1 2 : absolute maximum ratings for gtp transceivers (1) symbol description min max units mgtavcc analog supply voltage for the gtp transmitter and receiver circuits relative to gnd ?0.5 1.32 v mgtavtttx analog supply voltage for the gtp transmitte r termination circuit relative to gnd ?0.5 1.32 v mgtavttrx analog supply voltage for the gtp receiver termination circuit relative to gnd ?0.5 1.32 v mgtavccpll analog supply voltage for the gtp transmitter and receiver pll circuits relative to gnd ?0.5 1.32 v mgtavttrcal analog supply voltage for the resistor calibration circuit of the gtp transceiver bank (top or bottom) ?0.5 1.32 v v in receiver (rxp/rxn) and transmitter (txp/ txn) absolute input voltage ?0.5 1.32 v v mgtrefclk reference clock absolute input voltage ?0.5 1.32 v notes: 1. stresses beyond those listed under absolute maximum ratings mi ght cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions bey ond those listed under operating conditions is not impli ed. exposure to absolute maximum ratings conditions for extended perio ds of time might affect device reliability. ta bl e 1 3 : recommended operating conditions for gtp transceivers (1)(2)(3) symbol description min typ max units mgtavcc analog supply voltage for the gtp transmitter and receiver circuits relative to gnd 1.14 1.20 1.26 v mgtavtttx analog supply voltage for the gtp transmitter termination circuit relative to gnd 1.14 1.20 1.26 v mgtavttrx analog supply voltage for the gtp receiver termination circuit relative to gnd 1.14 1.20 1.26 v mgtavccpll analog supply voltage for the gtp trans mitter and receiver pll circuits relative to gnd 1.14 1.20 1.26 v mgtavttrcal analog supply voltage for the resistor calibration ci rcuit of the gtp transceiver bank (top or bottom) 1.14 1.20 1.26 v notes: 1. each voltage listed requires the filter circuit described in spartan-6 fpga gtp transceivers user guide . 2. voltages are specified for the temperature range of t j = ?40 ? c to +100 ? c. 3. the voltage level of mgtavccpll must not exceed the voltage level of mgtavcc +10mv. the voltage level of mgtavcc must not exce ed the voltage level of mgtavccpll.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 12 ta bl e 1 4 : gtp transceiver current supply (per lane) symbol description typ (1) max units i mgtavcc gtp transceiver internal analog supply current 40.4 note 2 ma i mgtavtttx gtp transmitter termination supply current 27.4 ma i mgtavttrx gtp receiver termination supply current 13.6 ma i mgtavccpll gtp transmitter and receiver pll supply current 28.7 ma r mgtrref precision reference resistor for internal calibration termination 50.0 1% tolerance ? notes: 1. typical values are specified at nomi nal voltage, 25c, with a 2.5 gb/s line rate, with a shared pll use mode. 2. values for currents of other transceiver configurations and conditions can be obtai ned by using the xpower estimator (xpe) or xpower analyzer (xpa) tools. ta bl e 1 5 : gtp transceiver quiescent supply current (per lane) (1)(2)(3)(4) symbol description typ (5) max units i mgtavccq quiescent mgtavcc supply current 1.7 note 2 ma i mgtavtttxq quiescent mgtavtttx supply current 0.1 ma i mgtavttrxq quiescent mgtavttrx supply current 1.2 ma i mgtavccpllq quiescent mgtavccpll supply current 1.0 ma notes: 1. device powered and unconfigured. 2. currents for conditions other than values specified in this table can be obtained by using the xpower estimator (xpe) or xpow er analyzer (xpa) tools. 3. gtp transceiver quiescent supply current for an entire device ca n be calculated by multiplying the values in this table by th e number of available gtp transceivers. 4. does not include power-up mgtavttrcal supply current during device configuration. 5. typical values are specifi ed at nominal voltage, 25c.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 13 gtp transceiver dc input and output levels ta bl e 1 6 summarizes the dc output specifications of the gtp transceivers in spartan-6 fpgas. figure 1 shows the single- ended output voltage swing. figure 2 shows the peak-to-peak differential output voltage. consult ug386 : spartan-6 fpga gtp transceivers user guide for further details. ta bl e 1 7 summarizes the dc specifications of the clock input of the gtp transceiver. consult the spartan-6 fpga gtp transceivers user guide for further details. ta bl e 1 6 : gtp transceiver dc specifications symbol dc parameter conditions min typ max units dv ppin differential peak-to-peak input voltage external ac coupled 140 ? 2000 mv v in absolute input voltage dc coupled mgtavttrx = 1.2v ?400 ? mgtavttrx mv v cmin common mode input voltage dc coupled mgtavttrx = 1.2v ?3/4 mgtavttrx ?mv dv ppout differential peak-t o-peak output voltage (1) transmitter output swing is set to maximum setting ? ? 1000 mv v seout single-ended output voltage swing (1) ? ? 500 mv v cmoutdc common mode output voltage equation based mgtavtttx ? v seout /2 mv r in differential input resistance 80 100 130 ? r out differential output resistance 80 100 130 ? t oskew transmitter output skew ? ? 15 ps c ext recommended external ac coupling capacitor (2) 75 100 200 nf notes: 1. the output swing and preemphasis levels are prog rammable using the attributes discussed in the spartan-6 fpga gtp transceivers user guide and can result in values lower than reported in this table. 2. other values can be used as appropriate to conform to specific protocols and standards. x-ref target - figure 1 figure 1: single-ended peak-to-peak voltage x-ref target - figure 2 figure 2: differential peak-to-peak voltage 0 +v p n s ingle-ended volt a ge d s 162_01_112009 0 +v ?v p?n differenti a l volt a ge d s 162_02_112009
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 14 gtp transceiver switching characteristics consult the spartan-6 fpga gtp transceivers user guide for further information. ta bl e 1 7 : gtp transceiver clock dc input level specification symbol dc parameter min typ max units v idiff differential peak-to-peak input voltage 200 800 2000 mv r in differential input resistance 80 100 120 ? c ext required external ac coupling capacitor ? 100 ? nf ta bl e 1 8 : gtp transceiver performance symbol description speed grade units -3 -3n -2 -1l f gtpmax maximum gtp transceiver data rate 3.2 3.2 2.7 n/a gb/s f gtprange1 gtp transceiver data rate range when pll_txdivsel_out = 1 1.88 to 3.2 1.88 to 3.2 1.88 to 2.7 n/a gb/s f gtprange2 gtp transceiver data rate range when pll_txdivsel_out = 2 0.94 to 1.62 0.94 to 1.62 0.94 to 1.62 n/a gb/s f gtprange3 gtp transceiver data rate range when pll_txdivsel_out = 4 0.6 to 0.81 0.6 to 0. 81 0.6 to 0.81 n/a gb/s f gpllmax maximum pll frequency 1.62 1.62 1.62 n/a ghz f gpllmin minimum pll frequency 0.94 0.94 0.94 n/a ghz ta bl e 1 9 : gtp transceiver dynamic reconfiguration port (drp) switching characteristics symbol description speed grade units -3 -3n -2 -1l f gtpdrpclk gtp transceiver dclk (drp clock) maximum frequency 125 125 100 n/a mhz ta bl e 2 0 : gtp transceiver reference clock switching characteristics symbol description conditions all lxt speed grades units min typ max f gclk reference clock frequency range 60 ? 160 mhz t rclk reference clock rise time 20% ? 80% ? 200 ? ps t fclk reference clock fall time 80% ? 20% ? 200 ? ps t dcref reference clock duty cycle transceiver pll only 45 50 55 % t lock clock recovery frequency acquisition time initial pll lock ? ? 1 ms t phase clock recovery phase acquisition time lock to data after pll has locked to the reference clock ??200s x-ref target - figure 3 figure 3: reference clock timing parameters d s 162_05_042109 8 0 % 20 % t fclk t rclk
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 15 ta bl e 2 1 : gtp transceiver user clock switching characteristics (1) symbol description conditions speed grade units -3 -3n -2 -1l f txout txoutclk maximum frequency 320 320 270 n/a mhz f rxrec rxrecclk maximum frequency 320 320 270 n/a mhz t rx rxusrclk maximum frequency 320 320 270 n/a mhz t rx2 rxusrclk2 maximum frequency 1 byte interface 156.25 156.25 125 n/a mhz 2 byte interface 160 160 125 n/a mhz 4 byte interface 80 80 67.5 n/a mhz t tx txusrclk maximum frequency 320 320 270 n/a mhz t tx2 txusrclk2 maximum frequency 1 byte interface 156.25 156.25 125 n/a mhz 2 byte interface 160 160 125 n/a mhz 4 byte interface 80 80 67.5 n/a mhz notes: 1. clocking must be implemented as described in the spartan-6 fpga gtp transceivers user guide . ta bl e 2 2 : gtp transceiver transmitter switching characteristics symbol description condi tion min typ max units t rtx tx rise time 20%?80% ? 140 ? ps t ftx tx fall time 80%?20% ? 120 ? ps t llskew tx lane-to-lane skew (1) ? ? 400 ps v txoobvdpp electrical idle amplitude ? ? 20 mv t txoobtransition electrical idle transition time ? ? 50 ns t j3.125 total jitter (2) 3.125 gb/s ? ? 0.35 ui d j3.125 deterministic jitter (2) ? ? 0.15 ui t j2.5 total jitter (2) 2.5 gb/s ? ? 0.33 ui d j2.5 deterministic jitter (2) ? ? 0.15 ui t j1.62 total jitter (2) 1.62 gb/s ? ? 0.20 ui d j1.62 deterministic jitter (2) ? ? 0.10 ui t j1.25 total jitter (2) 1.25 gb/s ? ? 0.20 ui d j1.25 deterministic jitter (2) ? ? 0.10 ui t j614 total jitter (2) 614 mb/s ? ? 0.10 ui d j614 deterministic jitter (2) ? ? 0.05 ui notes: 1. using same refclk input with txenpmaphasealign enable d for up to four consecutive gtp transceiver sites. 2. using pll_divsel_fb = 2, intdatawidth = 1. these values are not intended for protocol specif ic compliance determinations.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 16 endpoint block for pci express de signs switching characteristics the endpoint block for pci express is available in the spartan-6 lxt family. consult the spartan-6 fpga integrated endpoint block for pci express for further information. ta bl e 2 3 : gtp transceiver receiver switching characteristics symbol description min typ max units t rxelecidle time for rxelecidle to respond to loss or restoration of data ? 75 ? ns r xoobvdpp oob detect threshold peak-to-peak 60 ? 150 mv r xsst receiver spread-spectrum tracking (1) modulated @ 33 khz ?5000 ? 0 ppm r xrl run length (cid) internal ac capacitor bypassed ? ? 150 ui r xppmtol data/refclk ppm offset tolerance cdr 2 nd -order loop disabled ?200 ? 200 ppm cdr 2 nd -order loop enabled pll_rxdivsel_out = 1 ?2000 ? 2000 ppm pll_rxdivsel_out = 2 ?2000 ? 2000 ppm pll_rxdivsel_out = 4 ?1000 ? 1000 ppm sj jitter tolerance (2) jt_sj 3.125 sinusoidal jitter (3) 3.125 gb/s 0.4 ? ? ui jt_sj 2.5 sinusoidal jitter (3) 2.5 gb/s 0.4 ? ? ui jt_sj 1.62 sinusoidal jitter (3) 1.62 gb/s 0.5 ? ? ui jt_sj 1.25 sinusoidal jitter (3) 1.25 gb/s 0.5 ? ? ui jt_sj 614 sinusoidal jitter (3) 614 mb/s 0.5 ? ? ui sj jitter tolerance with stressed eye (2)(5) jt_tjse 3.125 total jitter with stressed eye (4) 3.125 gb/s 0.65 ? ? ui jt_sjse 3.125 sinusoidal jitter with stressed eye 3.125 gb/s 0.1 ? ? ui jt_tjse 2.7 total jitter with stressed eye (4) 2.7 gb/s 0.65 ? ? ui jt_sjse 2.7 sinusoidal jitter with stressed eye 2.7 gb/s 0.1 ? ? ui notes: 1. using pll_rxdivsel_out = 1, 2, and 4. 2. all jitter values are based on a bit error ratio of 1e ?12 . 3. using 80 mhz sinusoidal jitter only in t he absence of deterministic and random jitter. 4. composed of 0.37 ui dj in the form of isi and 0.18 ui rj. 5. measured using prbs7 data pattern. ta bl e 2 4 : maximum performance for pci express designs symbol description speed grade units -3 -3n -2 -1l f pcieuser user clock maximum frequency 62.5 62.5 62.5 n/a mhz
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 17 performance characteristics this section provides the performance characteristics of some common functions and designs implemented in spartan-6 devices. the numbers reported here are worst-case values; they have all been fully characterized. these values are subject to the same guidelines as the switching characteristics, page 18 . ta bl e 2 5 : interface performances description i/o resource clock buffer data width speed grade units -3 -3n -2 -1l networking applications (1) sdr lvds transmitter or receiver iob sdr register bufg ? 400 400 375 250 mb/s ddr lvds transmitter or receiver oddr2/iddr2 register 2 bufgs ? 800 800 750 500 mb/s sdr lvds transmitter oserdes2 bufpll 2 500 500 500 ? mb/s 3 750 750 750 ? mb/s 4-8 1080 1050 950 500 mb/s ddr lvds transmitter oserdes2 2 bufio2s 2 500 500 500 ? mb/s 3 750 750 750 ? mb/s 4-8 1080 1050 950 500 mb/s sdr lvds receiver iserdes2 in retimed mode bufpll 2 500 500 500 ? mb/s 3 750 750 750 ? mb/s 4-8 1080 1050 950 500 mb/s ddr lvds receiver iserdes2 in retimed mode 2 bufio2s 2 500 500 500 ? mb/s 3 750 750 750 ? mb/s 4-8 1080 1050 950 500 mb/s memory interfaces (implemented using the spartan-6 fpga memory controller block) (2) standard performance (standard v ccint ) ddr 400 note 4 400 350 mb/s ddr2 667 note 4 625 400 mb/s ddr3 667 note 4 625 ? mb/s lpddr (mobile_ddr) 400 note 4 400 350 mb/s extended performance (requires exte nded memory controller block v ccint ) (3) ddr2 800 note 4 667 ? mb/s ddr3 800 note 4 667 ? mb/s notes: 1. refer to xapp1064 , source-synchronous serialization and deserialization (up to 1050 mb/s) and ug381 , spartan-6 fpga selectio resources user guide. 2. refer to ug388 , spartan-6 fpga memory controller user guide . 3. extended memory controller block performance for ddr2 and ddr3 can be achieved using the extended mcb performance v ccint range from ta bl e 2 . 4. the -3n speed grade does not support a memory controller block.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 18 switching characteristics all values represented in this data sheet are based on these speed specifications: v1.17 for -3, -3n, and -2; and v1.06 for -1l. switching characteristics are specified on a per-speed- grade basis and can be designated as advance, preliminary, or production. each designation is defined as follows: advance these specifications are based on simulations only and are typically available soon after device design specifications are frozen. although speed grades with this designation are considered relatively stable and conservative, some under- reporting might still occur. preliminary these specifications are based on complete es (engineering sample) silicon characterization. devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. the probability of under -reporting delays is greatly reduced as compared to advance data. production these specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal notification of any subsequent changes. typically, the slowest speed grades transition to production before faster speed grades. all specifications are always representative of worst-case supply voltage and junction temperature conditions. since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. the -1l speed grade refers to the lower-power spartan-6 devices. the -3n speed grade refers to the spartan-6 devices that do not support mcb functionality. ta b l e 2 6 correlates the current status of each spartan-6 device on a per speed grade basis. testing of switching characteristics all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. unless otherwise noted, values apply to all spartan-6 devices. table 26: spartan-6 device speed grade designations device speed grade designations advance preliminary production xc6slx4 (1) -1l -3, -2 xc6slx9 -1l -3, -3n, -2 xc6slx16 -1l -3, -3n, -2 xc6slx25 -1l -3, -3n, -2 xc6slx25t -3, -3n, -2 xc6slx45 -3, -3n, -2, -1l xc6slx45t -3, -3n, -2 xc6slx75 -1l -3, -3n, -2 xc6slx75t -3, -3n, -2 xc6slx100 -1l -3, -3n, -2 xc6slx100t -3, -3n, -2 xc6slx150 -1l -3, -3n, -2 xc6slx150t -3, -3n, -2 notes: 1. the xc6slx4 is not available in the -3n speed grade.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 19 production silicon and ise software status in some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (advance, preliminary, production). any labeling discrepancies are corrected in subsequent speed specification releases. ta bl e 2 7 lists the production released spartan-6 family member, speed grade, and the minimum corresponding supported speed specification version and ise? software revisions. the ise software and speed specifications listed are the minimum releases required for production. all subsequent releases of software and speed specifications are valid. iob pad input/output/3-state switching characteristics ta bl e 2 8 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. t iopi is described as the delay from iob pad through the input buffer to the i-pin of an iob pad. the delay varies depending on th e capability of the selectio input buffer. t ioop is described as the delay from the o pin to the iob pad through the output buffer of an iob pad. the delay varies depending on the capability of th e selectio output buffer. t iotp is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is disabled. the delay varies depending on the selectio capability of the output buffer. ta b l e 2 9 summarizes the value of t iotphz . t iotphz is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is enabled (i.e., a high impedance state). ta bl e 2 7 : spartan-6 device production software and speed specification release (1) device speed grade designations (2) -3 (3) -3n -2 (4) -1l xc6slx4 ise 12.4 v1.15 n/a ise 12.3 v1.12 (5) xc6slx9 ise 12.4 v1.15 ise 12.4 v1.15 ise 12.3 v1.12 (5) xc6slx16 ise 12.1 v1.08 ise 12.2 v1.11 (6) ise 11.5 v1.06 xc6slx25 ise 12.2 v1.11 (6) xc6slx25t ise 12.2 v1.11 (6) n/a xc6slx45 ise 12.1 v1.08 ise 12.2 v1.11 (6) ise 11.5 v1.07 ise 13.1 v1.06 xc6slx45t ise 12.1 v1.08 ise 12.2 v1.11 (6) ise 12.1 v1.08 n/a xc6slx75 ise 12.2 v1.11 (6) xc6slx75t ise 12.2 v1.11 (6) n/a xc6slx100 ise 12.2 v1.11 (6) xc6slx100t ise 12.2 v1.11 (6) n/a xc6slx150 ise 12.2 v1.11 (6) xc6slx150t ise 12.2 v1.11 (6) n/a notes: 1. blank entries indicate a device and/or s peed grade in advance or preliminary status. 2. as marked with an n/a, lxt devices are not available with a -1l speed grade; lx4 devices are not available with a -3n speed g rade. 3. improved -3 specifications reflected in this data sheet require ise 12.4 so ftware with v1.15 speed specification. 4. improved -2 specifications reflected in th is data sheet require ise 12.4 software and the 12.4 speed files patch which contains the v1.17 speed specification available on the xilinx download center . 5. ise 12.3 software with v1.12 speed specificat ion is available using ise 12.3 software and the 12.3 speed files patch available on the xilinx download center . 6. ise 12.2 software with v1.11 speed specificat ion is available using ise 12.2 software and the 12.2 speed files patch available on the xilinx download center .
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 20 ta bl e 2 8 : iob switching characteristics i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -3n -2 -1l -3 -3n -2 -1l -3 -3n -2 -1l lvds_33 1.17 1.29 1.42 1.68 1.55 1.69 1.89 2.42 3000 3000 3000 3000 ns lvds_25 1.01 1.13 1.26 1.57 1.65 1.79 1.99 2.47 3000 3000 3000 3000 ns blvds_25 1.02 1.14 1.27 1.57 1.72 1. 86 2.06 2.68 1.72 1.86 2.06 2.68 ns mini_lvds_33 1.17 1.29 1.42 1.68 1. 57 1.71 1.91 2.41 3000 3000 3000 3000 ns mini_lvds_25 1.01 1.13 1.26 1.57 1. 65 1.79 1.99 2.47 3000 3000 3000 3000 ns lvpecl_33 1.18 1.30 1.43 1.68 n/a n/a n/a n/a n/a n/a n/a n/a ns lvpecl_25 1.02 1.14 1.27 1.57 n/a n/a n/a n/a n/a n/a n/a n/a ns rsds_33 (point to point) 1.17 1.29 1.42 1.68 1.57 1.71 1.91 2.42 3000 3000 3000 3000 ns rsds_25 (point to point) 1.01 1.13 1.26 1.56 1.65 1.79 1.99 2.47 3000 3000 3000 3000 ns tmds_33 1.21 1.33 1.46 1.71 1.54 1.68 1.88 2.50 3000 3000 3000 3000 ns ppds_33 1.17 1.29 1.42 1.68 1.57 1.71 1.91 2.43 3000 3000 3000 3000 ns ppds_25 1.01 1.13 1.26 1.56 1.68 1.82 2.02 2.47 3000 3000 3000 3000 ns pci33_3 1.07 1.19 1.32 1.57 (1) 3.51 3.65 3.85 4.38 (1) 3.51 3.65 3.85 4.38 (1) ns pci66_3 1.07 1.19 1.32 1.57 (1) 3.53 3.67 3.87 4.39 (1) 3.53 3.67 3.87 4.39 (1) ns display_port 1.02 1.14 1.27 1.56 3.15 3.29 3.49 4.08 3.15 3.29 3.49 4.08 ns i2c 1.33 1.45 1.58 1.82 11.56 11.70 11 .90 12.52 11.56 11.70 11.90 12.52 ns smbus 1.33 1.45 1.58 1.82 11.56 11.70 11.90 12.52 11.56 11.70 11.90 12.52 ns sdio 1.36 1.48 1.61 1.84 2.64 2.78 2.98 3.60 2.64 2.78 2.98 3.60 ns mobile_ddr 0.94 1.06 1.19 1.43 2.35 2.49 2.69 3.31 2.35 2.49 2.69 3.31 ns hstl_i 0.90 1.02 1.15 1.39 1.66 1. 80 2.00 2.62 1.66 1.80 2.00 2.62 ns hstl_ii 0.91 1.03 1.16 1.40 1.72 1.86 2.06 2.68 1.72 1.86 2.06 2.68 ns hstl_iii 0.95 1.07 1.20 1.44 1.67 1. 81 2.01 2.61 1.67 1.81 2.01 2.61 ns hstl_i _18 0.94 1.06 1.19 1.43 1.77 1.91 2.11 2.73 1.77 1.91 2.11 2.73 ns hstl_ii _18 0.94 1.06 1.19 1.43 1.85 1 .99 2.19 2.81 1.85 1.99 2.19 2.81 ns hstl_iii _18 0.99 1.11 1.24 1.47 1.79 1.93 2.13 2.72 1.79 1.93 2.13 2.72 ns sstl3_i 1.58 1.70 1.83 2.16 1.83 1. 97 2.17 2.72 1.83 1.97 2.17 2.72 ns sstl3_ii 1.58 1.70 1.83 2.16 2.01 2.15 2.35 2.94 2.01 2.15 2.35 2.94 ns sstl2_i 1.30 1.42 1.55 1.87 1.77 1. 91 2.11 2.69 1.77 1.91 2.11 2.69 ns sstl2_ii 1.30 1.42 1.55 1.88 1.86 2.00 2.20 2.82 1.86 2.00 2.20 2.82 ns sstl18_i 0.92 1.04 1.17 1.41 1.63 1.77 1.97 2.59 1.63 1.77 1.97 2.59 ns sstl18_ii 0.92 1.04 1.17 1.41 1.66 1. 80 2.00 2.62 1.66 1.80 2.00 2.62 ns sstl15_ii 0.92 1.04 1.17 1.41 1.67 1. 81 2.01 2.63 1.67 1.81 2.01 2.63 ns diff_hstl_i 0.94 1.06 1. 19 1.46 1.77 1.91 2.11 2.62 1.77 1.91 2.11 2.62 ns diff_hstl_ii 0.93 1.05 1.18 1.45 1.72 1.86 2.06 2.54 1.72 1.86 2.06 2.54 ns diff_hstl_iii 0.93 1.05 1.18 1.46 1.69 1.83 2.03 2.53 1.69 1.83 2.03 2.53 ns diff_hstl_i_18 0.97 1.09 1.22 1.50 1.79 1.93 2.13 2.63 1.79 1.93 2.13 2.63 ns diff_hstl_ii_18 0.97 1.09 1.22 1.49 1.69 1.83 2.03 2. 51 1.69 1.83 2.03 2.51 ns diff_hstl_iii_18 0.97 1.09 1.22 1.50 1.6 9 1.83 2.03 2.53 1.69 1.83 2.03 2.53 ns
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 21 diff_sstl3_i 1.18 1.30 1. 43 1.68 1.81 1.95 2.15 2.64 1.81 1.95 2.15 2.64 ns diff_sstl3_ii 1.19 1.31 1.44 1.68 1.80 1.94 2.14 2.63 1.80 1.94 2.14 2.63 ns diff_sstl2_i 1.02 1.14 1. 27 1.57 1.80 1.94 2.14 2.62 1.80 1.94 2.14 2.62 ns diff_sstl2_ii 1.02 1.14 1.27 1.57 1.76 1.90 2.10 2.57 1.76 1.90 2.10 2.57 ns diff_sstl18_i 0.97 1.09 1.22 1.51 1.72 1.86 2.06 2.56 1.72 1.86 2.06 2.56 ns diff_sstl18_ii 0.98 1.10 1. 23 1.50 1.68 1.82 2.02 2.52 1.68 1.82 2.02 2.52 ns diff_sstl15_ii 0.94 1.06 1. 19 1.46 1.67 1.81 2.01 2.50 1.67 1.81 2.01 2.50 ns diff_mobile_ddr 0.97 1.09 1.22 1.51 1. 75 1.89 2.09 2.57 1.75 1.89 2.09 2.57 ns lvttl, quietio, 2 ma 1.35 1.47 1.60 1.82 5.39 5.53 5.73 6.37 5.39 5.53 5.73 6.37 ns lvttl, quietio, 4 ma 1.35 1.47 1.60 1.82 4.29 4.43 4.63 5.22 4.29 4.43 4.63 5.22 ns lvttl, quietio, 6 ma 1.35 1.47 1.60 1.82 3.75 3.89 4.09 4.69 3.75 3.89 4.09 4.69 ns lvttl, quietio, 8 ma 1.35 1.47 1.60 1.82 3.23 3.37 3.57 4.20 3.23 3.37 3.57 4.20 ns lvttl, quietio, 12 ma 1.35 1.47 1.60 1. 82 3.28 3.42 3.62 4.22 3.28 3.42 3.62 4.22 ns lvttl, quietio, 16 ma 1.35 1.47 1.60 1. 82 2.94 3.08 3.28 3.92 2.94 3.08 3.28 3.92 ns lvttl, quietio, 24 ma 1.35 1.47 1.60 1. 82 2.69 2.83 3.03 3.67 2.69 2.83 3.03 3.67 ns lvttl, slow, 2 ma 1.35 1.47 1.60 1.82 4.36 4.50 4.70 5.30 4.36 4.50 4.70 5.30 ns lvttl, slow, 4 ma 1.35 1.47 1.60 1.82 3.17 3.31 3.51 4.16 3.17 3.31 3.51 4.16 ns lvttl, slow, 6 ma 1.35 1.47 1.60 1.82 2.76 2.90 3.10 3.75 2.76 2.90 3.10 3.75 ns lvttl, slow, 8 ma 1.35 1.47 1.60 1.82 2.59 2.73 2.93 3.55 2.59 2.73 2.93 3.55 ns lvttl, slow, 12 ma 1.35 1.47 1.60 1.82 2.58 2.72 2.92 3.54 2.58 2.72 2.92 3.54 ns lvttl, slow, 16 ma 1.35 1.47 1.60 1.82 2.39 2.53 2.73 3.40 2.39 2.53 2.73 3.40 ns lvttl, slow, 24 ma 1.35 1.47 1.60 1.82 2.28 2.42 2.62 3.24 2.28 2.42 2.62 3.24 ns lvttl, fast, 2 ma 1.35 1.47 1.60 1.82 3.78 3.92 4.12 4.74 3.78 3.92 4.12 4.74 ns lvttl, fast, 4 ma 1.35 1.47 1.60 1.82 2.49 2.63 2.83 3.45 2.49 2.63 2.83 3.45 ns lvttl, fast, 6 ma 1.35 1.47 1.60 1.82 2.44 2.58 2.78 3.40 2.44 2.58 2.78 3.40 ns lvttl, fast, 8 ma 1.35 1.47 1.60 1.82 2.32 2.46 2.66 3.28 2.32 2.46 2.66 3.28 ns lvttl, fast, 12 ma 1.35 1.47 1.60 1.82 1.83 1.97 2.17 2.79 1.83 1.97 2.17 2.79 ns lvttl, fast, 16 ma 1.35 1.47 1.60 1.82 1.83 1.97 2.17 2.79 1.83 1.97 2.17 2.79 ns lvttl, fast, 24 ma 1.35 1.47 1.60 1.82 1.83 1.97 2.17 2.79 1.83 1.97 2.17 2.79 ns lvcmos33, quietio, 2 ma 1.34 1.46 1.59 1.8 2 5.40 5.54 5.74 6.37 5.40 5.54 5.74 6.37 ns lvcmos33, quietio, 4 ma 1.34 1.46 1.59 1.8 2 4.03 4.17 4.37 5.01 4.03 4.17 4.37 5.01 ns lvcmos33, quietio, 6 ma 1.34 1.46 1.59 1.8 2 3.51 3.65 3.85 4.47 3.51 3.65 3.85 4.47 ns lvcmos33, quietio, 8 ma 1.34 1.46 1.59 1.8 2 3.37 3.51 3.71 4.33 3.37 3.51 3.71 4.33 ns lvcmos33, quietio, 12 ma 1.34 1.46 1.59 1. 82 2.94 3.08 3.28 3.93 2.94 3.08 3.28 3.93 ns lvcmos33, quietio, 16 ma 1.34 1.46 1.59 1. 82 2.77 2.91 3.11 3.78 2.77 2.91 3.11 3.78 ns lvcmos33, quietio, 24 ma 1.34 1.46 1.59 1. 82 2.59 2.73 2.93 3.58 2.59 2.73 2.93 3.58 ns lvcmos33, slow, 2 ma 1.34 1.46 1.59 1.82 4 .37 4.51 4.71 5.28 4.37 4.51 4.71 5.28 ns lvcmos33, slow, 4 ma 1.34 1.46 1.59 1.82 2 .98 3.12 3.32 3.94 2.98 3.12 3.32 3.94 ns ta bl e 2 8 : iob switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -3n -2 -1l -3 -3n -2 -1l -3 -3n -2 -1l
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 22 lvcmos33, slow, 6 ma 1.34 1.46 1.59 1.82 2 .58 2.72 2.92 3.61 2.58 2.72 2.92 3.61 ns lvcmos33, slow, 8 ma 1.34 1.46 1.59 1.82 2 .65 2.79 2.99 3.61 2.65 2.79 2.99 3.61 ns lvcmos33, slow, 12 ma 1.34 1.46 1.59 1.82 2.39 2.53 2.73 3.31 2.39 2.53 2.73 3.31 ns lvcmos33, slow, 16 ma 1.34 1.46 1.59 1.82 2.31 2.45 2.65 3.27 2.31 2.45 2.65 3.27 ns lvcmos33, slow, 24 ma 1.34 1.46 1.59 1.82 2.28 2.42 2.62 3.24 2.28 2.42 2.62 3.24 ns lvcmos33, fast, 2 ma 1.34 1.46 1.59 1.82 3 .76 3.90 4.10 4.70 3.76 3.90 4.10 4.70 ns lvcmos33, fast, 4 ma 1.34 1.46 1.59 1.82 2 .48 2.62 2.82 3.44 2.48 2.62 2.82 3.44 ns lvcmos33, fast, 6 ma 1.34 1.46 1.59 1.82 2 .32 2.46 2.66 3.28 2.32 2.46 2.66 3.28 ns lvcmos33, fast, 8 ma 1.34 1.46 1.59 1.82 2 .07 2.21 2.41 3.03 2.07 2.21 2.41 3.03 ns lvcmos33, fast, 12 ma 1.34 1.46 1.59 1.82 1.65 1.79 1.99 2.62 1.65 1.79 1.99 2.62 ns lvcmos33, fast, 16 ma 1.34 1.46 1.59 1.82 1.65 1.79 1.99 2.62 1.65 1.79 1.99 2.62 ns lvcmos33, fast, 24 ma 1.34 1.46 1.59 1.82 1.65 1.79 1.99 2.62 1.65 1.79 1.99 2.62 ns lvcmos25, quietio, 2 ma 0.82 0.94 1.07 1.3 1 4.81 4.95 5.15 5.79 4.81 4.95 5.15 5.79 ns lvcmos25, quietio, 4 ma 0.82 0.94 1.07 1.3 1 3.70 3.84 4.04 4.66 3.70 3.84 4.04 4.66 ns lvcmos25, quietio, 6 ma 0.82 0.94 1.07 1.3 1 3.46 3.60 3.80 4.38 3.46 3.60 3.80 4.38 ns lvcmos25, quietio, 8 ma 0.82 0.94 1.07 1.3 1 3.20 3.34 3.54 4.12 3.20 3.34 3.54 4.12 ns lvcmos25, quietio, 12 ma 0.82 0.94 1.07 1. 31 2.83 2.97 3.17 3.75 2.83 2.97 3.17 3.75 ns lvcmos25, quietio, 16 ma 0.82 0.94 1.07 1. 31 2.64 2.78 2.98 3.64 2.64 2.78 2.98 3.64 ns lvcmos25, quietio, 24 ma 0.82 0.94 1.07 1. 31 2.45 2.59 2.79 3.42 2.45 2.59 2.79 3.42 ns lvcmos25, slow, 2 ma 0.82 0.94 1.07 1.31 3 .78 3.92 4.12 4.76 3.78 3.92 4.12 4.76 ns lvcmos25, slow, 4 ma 0.82 0.94 1.07 1.31 2 .79 2.93 3.13 3.73 2.79 2.93 3.13 3.73 ns lvcmos25, slow, 6 ma 0.82 0.94 1.07 1.31 2 .73 2.87 3.07 3.66 2.73 2.87 3.07 3.66 ns lvcmos25, slow, 8 ma 0.82 0.94 1.07 1.31 2 .48 2.62 2.82 3.42 2.48 2.62 2.82 3.42 ns lvcmos25, slow, 12 ma 0.82 0.94 1.07 1.31 2.01 2.15 2.35 2.95 2.01 2.15 2.35 2.95 ns lvcmos25, slow, 16 ma 0.82 0.94 1.07 1.31 2.01 2.15 2.35 2.95 2.01 2.15 2.35 2.95 ns lvcmos25, slow, 24 ma 0.82 0.94 1.07 1.31 2.01 2.15 2.35 2.94 2.01 2.15 2.35 2.94 ns lvcmos25, fast, 2 ma 0.82 0.94 1.07 1.31 3 .35 3.49 3.69 4.31 3.35 3.49 3.69 4.31 ns lvcmos25, fast, 4 ma 0.82 0.94 1.07 1.31 2 .25 2.39 2.59 3.22 2.25 2.39 2.59 3.22 ns lvcmos25, fast, 6 ma 0.82 0.94 1.07 1.31 2 .09 2.23 2.43 3.05 2.09 2.23 2.43 3.05 ns lvcmos25, fast, 8 ma 0.82 0.94 1.07 1.31 2 .02 2.16 2.36 2.98 2.02 2.16 2.36 2.98 ns lvcmos25, fast, 12 ma 0.82 0.94 1.07 1.31 1.56 1.70 1.90 2.52 1.56 1.70 1.90 2.52 ns lvcmos25, fast, 16 ma 0.82 0.94 1.07 1.31 1.56 1.70 1.90 2.52 1.56 1.70 1.90 2.52 ns lvcmos25, fast, 24 ma 0.82 0.94 1.07 1.31 1.56 1.70 1.90 2.52 1.56 1.70 1.90 2.52 ns lvcmos18, quietio, 2 ma 1.18 1.30 1.43 2.0 4 5.92 6.06 6.26 6.80 5.92 6.06 6.26 6.80 ns lvcmos18, quietio, 4 ma 1.18 1.30 1.43 2.0 4 4.74 4.88 5.08 5.63 4.74 4.88 5.08 5.63 ns lvcmos18, quietio, 6 ma 1.18 1.30 1.43 2.0 4 4.05 4.19 4.39 4.96 4.05 4.19 4.39 4.96 ns lvcmos18, quietio, 8 ma 1.18 1.30 1.43 2.0 4 3.71 3.85 4.05 4.63 3.71 3.85 4.05 4.63 ns lvcmos18, quietio, 12 ma 1.18 1.30 1.43 2. 04 3.35 3.49 3.69 4.27 3.35 3.49 3.69 4.27 ns ta bl e 2 8 : iob switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -3n -2 -1l -3 -3n -2 -1l -3 -3n -2 -1l
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 23 lvcmos18, quietio, 16 ma 1.18 1.30 1.43 2. 04 3.20 3.34 3.54 4.14 3.20 3.34 3.54 4.14 ns lvcmos18, quietio, 24 ma 1.18 1.30 1.43 2. 04 2.96 3.10 3.30 3.98 2.96 3.10 3.30 3.98 ns lvcmos18, slow, 2 ma 1.18 1.30 1.43 2.04 4 .62 4.76 4.96 5.54 4.62 4.76 4.96 5.54 ns lvcmos18, slow, 4 ma 1.18 1.30 1.43 2.04 3 .69 3.83 4.03 4.60 3.69 3.83 4.03 4.60 ns lvcmos18, slow, 6 ma 1.18 1.30 1.43 2.04 3 .00 3.14 3.34 3.94 3.00 3.14 3.34 3.94 ns lvcmos18, slow, 8 ma 1.18 1.30 1.43 2.04 2 .19 2.33 2.53 3.17 2.19 2.33 2.53 3.17 ns lvcmos18, slow, 12 ma 1.18 1.30 1.43 2.04 1.99 2.13 2.33 2.95 1.99 2.13 2.33 2.95 ns lvcmos18, slow, 16 ma 1.18 1.30 1.43 2.04 1.99 2.13 2.33 2.95 1.99 2.13 2.33 2.95 ns lvcmos18, slow, 24 ma 1.18 1.30 1.43 2.04 1.99 2.13 2.33 2.95 1.99 2.13 2.33 2.95 ns lvcmos18, fast, 2 ma 1.18 1.30 1.43 2.04 3 .59 3.73 3.93 4.53 3.59 3.73 3.93 4.53 ns lvcmos18, fast, 4 ma 1.18 1.30 1.43 2.04 2 .39 2.53 2.73 3.35 2.39 2.53 2.73 3.35 ns lvcmos18, fast, 6 ma 1.18 1.30 1.43 2.04 1 .88 2.02 2.22 2.84 1.88 2.02 2.22 2.84 ns lvcmos18, fast, 8 ma 1.18 1.30 1.43 2.04 1 .81 1.95 2.15 2.77 1.81 1.95 2.15 2.77 ns lvcmos18, fast, 12 ma 1.18 1.30 1.43 2.04 1.71 1.85 2.05 2.67 1.71 1.85 2.05 2.67 ns lvcmos18, fast, 16 ma 1.18 1.30 1.43 2.04 1.71 1.85 2.05 2.67 1.71 1.85 2.05 2.67 ns lvcmos18, fast, 24 ma 1.18 1.30 1.43 2.04 1.71 1.85 2.05 2.67 1.71 1.85 2.05 2.67 ns lvcmos18_jedec, quietio, 2 ma 0.94 1.06 1.19 1.41 5.91 6.05 6.25 6.79 5.91 6.05 6.25 6.79 ns lvcmos18_jedec, quietio, 4 ma 0.94 1.06 1.19 1.41 4.75 4.89 5.09 5.64 4.75 4.89 5.09 5.64 ns lvcmos18_jedec, quietio, 6 ma 0.94 1.06 1.19 1.41 4.04 4.18 4.38 4.96 4.04 4.18 4.38 4.96 ns lvcmos18_jedec, quietio, 8 ma 0.94 1.06 1.19 1.41 3.71 3.85 4.05 4.62 3.71 3.85 4.05 4.62 ns lvcmos18_jedec, quietio, 12 ma 0.94 1.06 1. 19 1.41 3.35 3.49 3.69 4.28 3.35 3.49 3.69 4.28 ns lvcmos18_jedec, quietio, 16 ma 0.94 1.06 1. 19 1.41 3.20 3.34 3.54 4.13 3.20 3.34 3.54 4.13 ns lvcmos18_jedec, quietio, 24 ma 0.94 1.06 1. 19 1.41 2.96 3.10 3.30 3.98 2.96 3.10 3.30 3.98 ns lvcmos18_jedec, slow, 2 ma 0.94 1.06 1.19 1 .41 4.59 4.73 4.93 5.54 4.59 4.73 4.93 5.54 ns lvcmos18_jedec, slow, 4 ma 0.94 1.06 1.19 1 .41 3.69 3.83 4.03 4.60 3.69 3.83 4.03 4.60 ns lvcmos18_jedec, slow, 6 ma 0.94 1.06 1.19 1 .41 3.00 3.14 3.34 3.94 3.00 3.14 3.34 3.94 ns lvcmos18_jedec, slow, 8 ma 0.94 1.06 1.19 1 .41 2.19 2.33 2.53 3.18 2.19 2.33 2.53 3.18 ns lvcmos18_jedec, slow, 12 ma 0.94 1.06 1.19 1.41 1.99 2.13 2.33 2.95 1.99 2.13 2.33 2.95 ns lvcmos18_jedec, slow, 16 ma 0.94 1.06 1.19 1.41 1.99 2.13 2.33 2.95 1.99 2.13 2.33 2.95 ns lvcmos18_jedec, slow, 24 ma 0.94 1.06 1.19 1.41 1.99 2.13 2.33 2.95 1.99 2.13 2.33 2.95 ns lvcmos18_jedec, fast, 2 ma 0.94 1.06 1.19 1.41 3.57 3.71 3.91 4.52 3.57 3.71 3.91 4.52 ns lvcmos18_jedec, fast, 4 ma 0.94 1.06 1.19 1.41 2.39 2.53 2.73 3.35 2.39 2.53 2.73 3.35 ns lvcmos18_jedec, fast, 6 ma 0.94 1.06 1.19 1.41 1.88 2.02 2.22 2.84 1.88 2.02 2.22 2.84 ns lvcmos18_jedec, fast, 8 ma 0.94 1.06 1.19 1.41 1.80 1.94 2.14 2.76 1.80 1.94 2.14 2.76 ns lvcmos18_jedec, fast, 12 ma 0.94 1.06 1.19 1.41 1.72 1.86 2.06 2.68 1.72 1.86 2.06 2.68 ns lvcmos18_jedec, fast, 16 ma 0.94 1.06 1.19 1.41 1.72 1.86 2.06 2.68 1.72 1.86 2.06 2.68 ns lvcmos18_jedec, fast, 24 ma 0.94 1.06 1.19 1.41 1.72 1.86 2.06 2.68 1.72 1.86 2.06 2.68 ns ta bl e 2 8 : iob switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -3n -2 -1l -3 -3n -2 -1l -3 -3n -2 -1l
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 24 lvcmos15, quietio, 2 ma 0.98 1.10 1.23 1.7 9 5.47 5.61 5.81 6.38 5.47 5.61 5.81 6.38 ns lvcmos15, quietio, 4 ma 0.98 1.10 1.23 1.7 9 4.61 4.75 4.95 5.51 4.61 4.75 4.95 5.51 ns lvcmos15, quietio, 6 ma 0.98 1.10 1.23 1.7 9 4.07 4.21 4.41 4.97 4.07 4.21 4.41 4.97 ns lvcmos15, quietio, 8 ma 0.98 1.10 1.23 1.7 9 3.91 4.05 4.25 4.81 3.91 4.05 4.25 4.81 ns lvcmos15, quietio, 12 ma 0.98 1.10 1.23 1. 79 3.53 3.67 3.87 4.51 3.53 3.67 3.87 4.51 ns lvcmos15, quietio, 16 ma 0.98 1.10 1.23 1. 79 3.32 3.46 3.66 4.31 3.32 3.46 3.66 4.31 ns lvcmos15, slow, 2 ma 0.98 1.10 1.23 1.79 4 .18 4.32 4.52 5.11 4.18 4.32 4.52 5.11 ns lvcmos15, slow, 4 ma 0.98 1.10 1.23 1.79 3 .42 3.56 3.76 4.34 3.42 3.56 3.76 4.34 ns lvcmos15, slow, 6 ma 0.98 1.10 1.23 1.79 2 .29 2.43 2.63 3.24 2.29 2.43 2.63 3.24 ns lvcmos15, slow, 8 ma 0.98 1.10 1.23 1.79 2 .30 2.44 2.64 3.25 2.30 2.44 2.64 3.25 ns lvcmos15, slow, 12 ma 0.98 1.10 1.23 1.79 2.03 2.17 2.37 2.99 2.03 2.17 2.37 2.99 ns lvcmos15, slow, 16 ma 0.98 1.10 1.23 1.79 2.01 2.15 2.35 2.97 2.01 2.15 2.35 2.97 ns lvcmos15, fast, 2 ma 0.98 1.10 1.23 1.79 3 .29 3.43 3.63 4.24 3.29 3.43 3.63 4.24 ns lvcmos15, fast, 4 ma 0.98 1.10 1.23 1.79 2 .27 2.41 2.61 3.22 2.27 2.41 2.61 3.22 ns lvcmos15, fast, 6 ma 0.98 1.10 1.23 1.79 1 .78 1.92 2.12 2.74 1.78 1.92 2.12 2.74 ns lvcmos15, fast, 8 ma 0.98 1.10 1.23 1.79 1 .73 1.87 2.07 2.69 1.73 1.87 2.07 2.69 ns lvcmos15, fast, 12 ma 0.98 1.10 1.23 1.79 1.73 1.87 2.07 2.64 1.73 1.87 2.07 2.64 ns lvcmos15, fast, 16 ma 0.98 1.10 1.23 1.79 1.73 1.87 2.07 2.64 1.73 1.87 2.07 2.64 ns lvcmos15_jedec, quietio, 2 ma 1.03 1.15 1.28 1.49 5.49 5.63 5.83 6.37 5.49 5.63 5.83 6.37 ns lvcmos15_jedec, quietio, 4 ma 1.03 1.15 1.28 1.49 4.61 4.75 4.95 5.51 4.61 4.75 4.95 5.51 ns lvcmos15_jedec, quietio, 6 ma 1.03 1.15 1.28 1.49 4.07 4.21 4.41 4.97 4.07 4.21 4.41 4.97 ns lvcmos15_jedec, quietio, 8 ma 1.03 1.15 1.28 1.49 3.92 4.06 4.26 4.81 3.92 4.06 4.26 4.81 ns lvcmos15_jedec, quietio, 12 ma 1.03 1.15 1. 28 1.49 3.54 3.68 3.88 4.51 3.54 3.68 3.88 4.51 ns lvcmos15_jedec, quietio, 16 ma 1.03 1.15 1. 28 1.49 3.33 3.47 3.67 4.31 3.33 3.47 3.67 4.31 ns lvcmos15_jedec, slow, 2 ma 1.03 1.15 1.28 1 .49 4.18 4.32 4.52 5.13 4.18 4.32 4.52 5.13 ns lvcmos15_jedec, slow, 4 ma 1.03 1.15 1.28 1 .49 3.42 3.56 3.76 4.35 3.42 3.56 3.76 4.35 ns lvcmos15_jedec, slow, 6 ma 1.03 1.15 1.28 1 .49 2.29 2.43 2.63 3.25 2.29 2.43 2.63 3.25 ns lvcmos15_jedec, slow, 8 ma 1.03 1.15 1.28 1 .49 2.30 2.44 2.64 3.26 2.30 2.44 2.64 3.26 ns lvcmos15_jedec, slow, 12 ma 1.03 1.15 1.28 1.49 2.01 2.15 2.35 2.97 2.01 2.15 2.35 2.97 ns lvcmos15_jedec, slow, 16 ma 1.03 1.15 1.28 1.49 2.01 2.15 2.35 2.97 2.01 2.15 2.35 2.97 ns lvcmos15_jedec, fast, 2 ma 1.03 1.15 1.28 1.49 3.28 3.42 3.62 4.22 3.28 3.42 3.62 4.22 ns lvcmos15_jedec, fast, 4 ma 1.03 1.15 1.28 1.49 2.27 2.41 2.61 3.23 2.27 2.41 2.61 3.23 ns lvcmos15_jedec, fast, 6 ma 1.03 1.15 1.28 1.49 1.78 1.92 2.12 2.74 1.78 1.92 2.12 2.74 ns lvcmos15_jedec, fast, 8 ma 1.03 1.15 1.28 1.49 1.73 1.87 2.07 2.69 1.73 1.87 2.07 2.69 ns lvcmos15_jedec, fast, 12 ma 1.03 1.15 1.28 1.49 1.73 1.87 2.07 2.63 1.73 1.87 2.07 2.63 ns lvcmos15_jedec, fast, 16 ma 1.03 1.15 1.28 1.49 1.73 1.87 2.07 2.63 1.73 1.87 2.07 2.63 ns lvcmos12, quietio, 2 ma 0.91 1.03 1.16 1.5 1 6.40 6.54 6.74 7.30 6.40 6.54 6.74 7.30 ns lvcmos12, quietio, 4 ma 0.91 1.03 1.16 1.5 1 4.98 5.12 5.32 5.90 4.98 5.12 5.32 5.90 ns ta bl e 2 8 : iob switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -3n -2 -1l -3 -3n -2 -1l -3 -3n -2 -1l
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 25 lvcmos12, quietio, 6 ma 0.91 1.03 1.16 1.5 1 4.65 4.79 4.99 5.55 4.65 4.79 4.99 5.55 ns lvcmos12, quietio, 8 ma 0.91 1.03 1.16 1.5 1 4.23 4.37 4.57 5.21 4.23 4.37 4.57 5.21 ns lvcmos12, quietio, 12 ma 0.91 1.03 1.16 1. 51 3.98 4.12 4.32 4.94 3.98 4.12 4.32 4.94 ns lvcmos12, slow, 2 ma 0.91 1.03 1.16 1.51 4 .98 5.12 5.32 5.91 4.98 5.12 5.32 5.91 ns lvcmos12, slow, 4 ma 0.91 1.03 1.16 1.51 2 .84 2.98 3.18 3.81 2.84 2.98 3.18 3.81 ns lvcmos12, slow, 6 ma 0.91 1.03 1.16 1.51 2 .77 2.91 3.11 3.72 2.77 2.91 3.11 3.72 ns lvcmos12, slow, 8 ma 0.91 1.03 1.16 1.51 2 .34 2.48 2.68 3.31 2.34 2.48 2.68 3.31 ns lvcmos12, slow, 12 ma 0.91 1.03 1.16 1.51 2.08 2.22 2.42 3.06 2.08 2.22 2.42 3.06 ns lvcmos12, fast, 2 ma 0.91 1.03 1.16 1.51 3 .46 3.60 3.80 4.44 3.46 3.60 3.80 4.44 ns lvcmos12, fast, 4 ma 0.91 1.03 1.16 1.51 2 .35 2.49 2.69 3.30 2.35 2.49 2.69 3.30 ns lvcmos12, fast, 6 ma 0.91 1.03 1.16 1.51 1 .79 1.93 2.13 2.75 1.79 1.93 2.13 2.75 ns lvcmos12, fast, 8 ma 0.91 1.03 1.16 1.51 1 .68 1.82 2.02 2.64 1.68 1.82 2.02 2.64 ns lvcmos12, fast, 12 ma 0.91 1.03 1.16 1.51 1.66 1.80 2.00 2.62 1.66 1.80 2.00 2.62 ns lvcmos12_jedec, quietio, 2 ma 1.50 1.62 1.75 1.88 6.39 6.53 6.73 7.31 6.39 6.53 6.73 7.31 ns lvcmos12_jedec, quietio, 4 ma 1.50 1.62 1.75 1.88 4.98 5.12 5.32 5.88 4.98 5.12 5.32 5.88 ns lvcmos12_jedec, quietio, 6 ma 1.50 1.62 1.75 1.88 4.67 4.81 5.01 5.54 4.67 4.81 5.01 5.54 ns lvcmos12_jedec, quietio, 8 ma 1.50 1.62 1.75 1.88 4.23 4.37 4.57 5.22 4.23 4.37 4.57 5.22 ns lvcmos12_jedec, quietio, 12 ma 1.50 1.62 1. 75 1.88 3.99 4.13 4.33 4.94 3.99 4.13 4.33 4.94 ns lvcmos12_jedec, slow, 2 ma 1.50 1.62 1.75 1 .88 5.00 5.14 5.34 5.90 5.00 5.14 5.34 5.90 ns lvcmos12_jedec, slow, 4 ma 1.50 1.62 1.75 1 .88 2.85 2.99 3.19 3.80 2.85 2.99 3.19 3.80 ns lvcmos12_jedec, slow, 6 ma 1.50 1.62 1.75 1 .88 2.76 2.90 3.10 3.72 2.76 2.90 3.10 3.72 ns lvcmos12_jedec, slow, 8 ma 1.50 1.62 1.75 1 .88 2.35 2.49 2.69 3.30 2.35 2.49 2.69 3.30 ns lvcmos12_jedec, slow, 12 ma 1.50 1.62 1.75 1.88 2.09 2.23 2.43 3.05 2.09 2.23 2.43 3.05 ns lvcmos12_jedec, fast, 2 ma 1.50 1.62 1.75 1.88 3.46 3.60 3.80 4.42 3.46 3.60 3.80 4.42 ns lvcmos12_jedec, fast, 4 ma 1.50 1.62 1.75 1.88 2.35 2.49 2.69 3.31 2.35 2.49 2.69 3.31 ns lvcmos12_jedec, fast, 6 ma 1.50 1.62 1.75 1.88 1.79 1.93 2.13 2.76 1.79 1.93 2.13 2.76 ns lvcmos12_jedec, fast, 8 ma 1.50 1.62 1.75 1.88 1.69 1.83 2.03 2.65 1.69 1.83 2.03 2.65 ns lvcmos12_jedec, fast, 12 ma 1.50 1.62 1.75 1.88 1.66 1.80 2.00 2.62 1.66 1.80 2.00 2.62 ns notes: 1. devices with a -1l speed grade do not support xilinx pci ip. ta bl e 2 9 : iob 3-state on output switching characteristics (t iotphz ) symbol description speed grade units -3 -3n -2 -1l t iotphz t input to pad high-impe dance 1.39 1.59 1.59 1.91 ns ta bl e 2 8 : iob switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -3n -2 -1l -3 -3n -2 -1l -3 -3n -2 -1l
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 26 i/o standard adjustment measurement methodology input delay measurements ta bl e 3 0 shows the test setup parameters used for measuring input delay. ta bl e 3 0 : input delay measurement methodology description i /o standard attribute v l (1) v h (1) v meas (3)(4) v ref (2)(4) lvttl (low-voltage transistor-transistor logic) lvttl 0 3.0 1.4 ? lvcmos (low-voltage cmos), 3.3v lvcmos33 0 3.3 1.65 ? lvcmos, 2.5v lvcmos25 0 2.5 1.25 ? lvcmos, 1.8v lvcmos18 0 1.8 0.9 ? lvcmos, 1.5v lvcmos15 0 1.5 0.75 ? lvcmos, 1.2v lvcmos12 0 1.2 0.6 ? pci (peripheral component interface), 33 mhz and 66 mhz, 3.3v pci33_3, pci66_3 per pci specification ? hstl (high-speed transceiver logic), class i & ii hstl_i, hstl_ii v ref ?0.5 v ref +0.5 v ref 0.75 hstl, class iii hstl_iii v ref ?0.5 v ref +0.5 v ref 0.90 hstl, class i & ii, 1.8v hstl_i_18, hstl_ii_18 v ref ?0.5 v ref +0.5 v ref 0.90 hstl, class iii 1.8v hstl_iii_18 v ref ?0.5 v ref +0.5 v ref 1.1 sstl (stub terminated transceiver logic), class i & ii, 3.3v sstl3_i, sstl3_ii v ref ?0.75 v ref +0.75 v ref 1.5 sstl, class i & ii, 2. 5v sstl2_i, sstl2_ii v ref ?0.75 v ref +0.75 v ref 1.25 sstl, class i & ii, 1.8v sstl18_i, sstl18_ii v ref ?0.5 v ref +0.5 v ref 0.90 sstl, class ii, 1.5v sstl15_ii v ref ?0.2 v ref +0.2 v ref 0.75 lvds (low-voltage differential signaling), 2.5v & 3.3v lvds_25, lvds_33 1.25 ? 0.125 1.25 + 0.125 0 (5) ? lvpecl (low-voltage positive emitter-coupled logic), 2.5v & 3.3v lvpecl_25, lvpecl_33 1.2 ? 0.3 1.2 ? 0.3 0 (5) ? blvds (bus lvds), 2.5v blvds_25 1.3 ? 0.125 1.3 + 0.125 0 (5) ? mini-lvds, 2.5v & 3.3v mini_lvds_25, mini_lvds_33 1.2 ? 0.125 1.2 + 0.125 0 (5) ? rsds (reduced swing differential signaling), 2.5v & 3.3v rsds_25, rsds_33 1.2 ? 0.1 1.2 + 0.1 0 (5) ? tmds (transition minimized differential signaling), 3.3v tmds_33 3.0 ? 0.1 3.0 + 0.1 0 (5) ? ppds (point-to-point differential signaling, 2.5v & 3.3v ppds_25, ppds_33 1.25 ? 0.1 1.25 + 0.1 0 (5) ? notes: 1. input waveform switches between v l and v h . 2. measurements are made at typical, minimum, and maximum v ref values. reported delays reflect worst case of these measurements. v ref values listed are typical. 3. input voltage level from which measurement starts. 4. this is an input voltage reference that bears no relation to the v ref / v meas parameters found in ibis models and/or noted in figure 4 . 5. the value given is the differential input voltage.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 27 output delay measurements output delays are measured using a tektronix p6245 tds500/600 probe (< 1 pf) across approximately 4" of fr4 microstrip trace. standard termination was used for all testing. the propagation delay of the 4" trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in figure 4 and figure 5 . measurements and test conditions are reflected in the ibis models except where the ibis format precludes it. parameters v ref , r ref , c ref , and v meas fully describe the test conditions for each i/o standard. the most accurate prediction of propagation delay in any given application can be obtained through ibis simulation, using the following method: 1. simulate the output driver of choice into the generalized test setup, using values from ta b l e 3 1 . 2. record the time to v meas . 3. simulate the output driver of choice into the actual pcb trace and load, using the appropriate ibis model or capacitance value to represent the load. 4. record the time to v meas . 5. compare the results of steps 2 and 4. the increase or decrease in delay yields the actual propagation delay of the pcb trace. x-ref target - figure 4 figure 4: single-ended test setup v ref r ref v mea s (volt a ge level when t a king del a y me asu rement) c ref (pro b e c a p a cit a nce) fpga o u tp u t d s 162_06_011 3 09 x-ref target - figure 5 figure 5: differential test setup r ref v mea s + ? c ref fpga o u tp u t d s 162_07_011 3 09 ta bl e 3 1 : output delay measurement methodology description i/o standard attribute r ref ( ? ) c ref (1) (pf) v meas (v) v ref (v) lvttl (low-voltage transistor-transistor logic) lvttl (all) 1m 0 1.4 0 lvcmos (low-voltage cmos), 3.3v lvcmos33 1m 0 1.65 0 lvcmos, 2.5v lvcmos25 1m 0 1.25 0 lvcmos, 1.8v lvcmos18 1m 0 0.9 0 lvcmos, 1.5v lvcmos15 1m 0 0.75 0 lvcmos, 1.2v lvcmos12 1m 0 0.75 0 pci (peripheral component interface) 33 mhz and 66 mhz, 3.3v pci33_3, pci66_3 (rising edge) 25 10 (2) 0.94 0 pci33_3, pci66_3 (falling edge) 25 10 (2) 2.03 3.3 hstl (high-speed transceiver logic), class i hstl_i 50 0 v ref 0.75 hstl, class ii hstl_ii 25 0 v ref 0.75 hstl, class iii hstl_iii 50 0 0.9 1.5 hstl, class i, 1.8v hstl_i_18 50 0 v ref 0.9 hstl, class ii, 1.8v hstl_ii_18 25 0 v ref 0.9 hstl, class iii, 1.8v hstl_iii_18 50 0 1.1 1.8 sstl (stub series terminated logic), class i, 1.8v sstl18_i 50 0 v ref 0.9 sstl, class ii, 1.8v sstl18_ii 25 0 v ref 0.9 sstl, class i, 2.5v sstl2_i 50 0 v ref 1.25
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 28 simultaneously switching outputs due to lead inductance, a given package supports a limited number of simultaneous switching outputs (ssos) when using fast, high-drive outputs. ta bl e 3 2 and ta b l e 3 3 provide guidelines for the recommended maximum allowable number of ssos. these guidelines describe the maximum number of user i/o pins of an output signal standard that should simultaneously switch in the same directio n, while maintaining a safe level of swit ching noise for that particular signal standard. meeting these guidelines for the stated test conditions ensures that the fpga operates free from the adverse effects of gnd and power bounce. for each device/package combination, ta bl e 3 2 provides the number of equivalent v cco /gnd pairs per bank. for each output signal standard and drive strength, ta bl e 3 3 recommends the maximum number of ssos, switching in the same direction, allowed per v cco /gnd pair within an i/o bank. the guidelines are categorized by package style, slew rate, and output drive current. the number of ssos are also specified by i/o bank. multiply the appropriate numbers from each table to calculate the maximum number of ssos allowed within an i/o bank. the guidelines assume that all pins within a bank use the same i/o standard. exceeding these sso guidelines can result in increased power or gnd bounce, degraded signal integrity, or increased system jitter. for a given i/o standard, if the sso limit per pair in ta bl e 3 3 is greater than the maximum i/o per pair in ta bl e 3 2 , then there is no sso limit for the exclusive use of that i/o standard. the recommended maximum sso values assume that the fpga is soldered on a printed circuit board and that the board uses sound design practices. due to the additional lead inductance introduced by the socket, the sso values do not apply for fpgas mounted in sockets. the sso values assume that the v ccaux is powered at 3.3v. setting v ccaux to 2.5v provides better sso characteristics. for more detail, see the spartan-6 fpga selectio resources user guide . sstl, class ii, 2.5v sstl2_ii 25 0 v ref 1.25 sstl, class ii, 1.5v sstl15_ii 25 0 v ref 0.75 lvds (low-voltage differential signal ing), 2.5v & 3.3v lvds_25, lvds_33 100 0 0 (3) 1.2 blvds (bus lvds), 2.5v blvds_25 100 0 0 (3) 0 mini-lvds, 2.5v & 3.3v mini_lvds_25, mini_lvds_33 100 0 0 (3) 1.2 rsds (reduced swing differential signalin g), 2.5v & 3.3v rsds_25, rsds_33 100 0 0 (3) 1.2 tmds (transition minimized differential signaling), 3.3v tmds_33 100 0 0 (3) ppds (point-to-point differential signaling, 2.5v & 3.3v ppds_25, ppds_33 100 0 0 (3) ? notes: 1. c ref is the capacitance of the probe, nominally 0 pf. 2. per pci specifications. 3. the value given is the differential output voltage. ta bl e 3 1 : output delay measurement methodology (cont?d) description i/o standard attribute r ref ( ? ) c ref (1) (pf) v meas (v) v ref (v)
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 29 ta bl e 3 2 : spartan-6 fpga v cco /gnd pairs per bank package devices description bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 tqg144 lx v cco /gnd pairs 3 32 3n/an/a maximum i/o per pair 8 813 8n/an/a cpg196 lx vcco/gnd pairs 4 64 6n/an/a maximum i/o per pair 6 47 4n/an/a csg225 lx v cco /gnd pairs 4 44 4n/an/a maximum i/o per pair 10 10 9 10 n/a n/a ft(g)256 lx v cco /gnd pairs 5 64 5n/an/a maximum i/o per pair 8 99 10 n/a n/a csg324 lx v cco /gnd pairs 6 66 6n/an/a maximum i/o per pair 10 910 9n/an/a lxt v cco /gnd pairs 4 66 6n/an/a maximum i/o per pair 4 910 9n/an/a csg484 lx v cco /gnd pairs 8 13 8 13 n/a n/a maximum i/o per pair 7 87 8n/an/a lxt v cco /gnd pairs 7 12 8 13 n/a n/a maximum i/o per pair 5 86 8n/an/a fg(g)484 lx v cco /gnd pairs 10 10 11 11 n/a n/a maximum i/o per pair 6 89 8n/an/a lxt v cco /gnd pairs 6 10 11 10 n/a n/a maximum i/o per pair 7 87 8n/an/a fg(g)676 lx45 v cco /gnd pairs 12 15 10 16 n/a n/a maximum i/o per pair 3 78 7n/an/a lx75, lx100, lx150 v cco /gnd pairs 12 910 10 6 6 maximum i/o per pair 9 10 9 989 lxt v cco /gnd pairs 10 810 877 maximum i/o per pair 8 78 877 fg(g)900 lx v cco /gnd pairs 17 14 17 14 7 8 maximum i/o per pair 7 67 876 lxt v cco /gnd pairs 15 14 13 14 7 8 maximum i/o per pair 7 68 876
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 30 ta bl e 3 3 : sso limit per v cco /gnd pair v cco i/o standard drive slew sso limit per v cco /gnd pair all tqg144, cpg196, csg225, ft(g)256, and lx devices in csg324 all csg484, fg(g)484, fg(g)676, fg(g)900, and lxt devices in csg324 bank 0/2 bank 1/3 bank 0/2 bank 1/3/4/5 1.2v lvcmos12, lvcmos12_jedec 2 fast 30 (1) 35 30 35 slow 51 55 51 52 quietio 71 58 71 70 4 fast 17 17 17 19 slow 23 25 23 22 quietio 35 32 35 32 6 fast 13 15 13 14 slow 19 20 19 17 quietio 26 24 26 24 8 fast n/a 12 n/a 12 slow n/a 15 n/a 13 quietio n/a 20 n/a 19 12 fast n/a 5 n/a 4 slow n/a 8 n/a 5 quietio n/a 11 n/a 10
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 31 1.5v lvcmos15, lvcmos15_jedec 2 fast 33 40 33 41 slow 57 62 57 56 quietio 70 67 70 66 4 fast 19 21 19 21 slow 30 30 30 24 quietio 38 33 38 30 6 fast 14 16 14 16 slow 18 19 18 17 quietio 27 24 27 21 8 fast 11 13 11 12 slow 16 16 16 14 quietio 23 20 23 17 12 fast n/a 5 n/a 4 slow n/a 8 n/a 5 quietio n/a 10 n/a 9 16 fast n/a 5 n/a 4 slow n/a 8 n/a 8 quietio n/a 10 n/a 9 hstl_i 9 10 9 10 hstl_ii n/a 5 n/a 6 hstl_iii 7 9 7 9 diff_hstl_i 27 30 27 30 diff_hstl_ii n/a 15 n/a 18 diff_hstl_iii 21 27 21 27 sstl_15_ii (3) n/a 5 n/a 4 diff_sstl_15_ii (3) n/a 15 n/a 12 ta bl e 3 3 : sso limit per v cco /gnd pair (cont?d) v cco i/o standard drive slew sso limit per v cco /gnd pair all tqg144, cpg196, csg225, ft(g)256, and lx devices in csg324 all csg484, fg(g)484, fg(g)676, fg(g)900, and lxt devices in csg324 bank 0/2 bank 1/3 bank 0/2 bank 1/3/4/5
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 32 1.8v lvcmos18, lvcmos18_jedec 2 fast 39 46 39 47 slow 65 75 65 74 quietio 80 80 80 85 4 fast 22 25 22 25 slow 38 36 38 29 quietio 45 40 45 35 6 fast 16 18 16 17 slow 27 25 27 19 quietio 30 28 30 23 8 fast 13 15 13 14 slow 16 18 16 16 quietio 25 22 25 18 12 fast 5 7 5 5 slow 7 8 7 6 quietio 11 10 11 8 16 fast 4 5 4 4 slow 7 8 7 5 quietio 11 10 11 8 24 fast n/a 5 n/a 3 slow n/a 8 n/a 8 quietio n/a 10 n/a 8 hstl_i_18 9 10 9 9 hstl_ii_18 n/a 5 n/a 6 hstl_iii_18 9 10 9 11 diff_hstl_i_18 27 30 27 27 diff_hstl_ii_18 n/a 15 n/a 18 diff_hstl_iii_18 27 30 27 33 mobile_ddr (3) 12 14 12 14 diff_mobile_ddr (3) 36 42 36 42 sstl_18_i (3) 9109 10 sstl_18_ii (3) n/a 5 n/a 4 diff_sstl_18_i (3) 27 30 27 30 diff_sstl_18_ii (3) n/a 15 n/a 12 ta bl e 3 3 : sso limit per v cco /gnd pair (cont?d) v cco i/o standard drive slew sso limit per v cco /gnd pair all tqg144, cpg196, csg225, ft(g)256, and lx devices in csg324 all csg484, fg(g)484, fg(g)676, fg(g)900, and lxt devices in csg324 bank 0/2 bank 1/3 bank 0/2 bank 1/3/4/5
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 33 2.5v lv c m o s 2 5 2 fast 38 43 38 43 slow 46 52 46 48 quietio 57 64 57 59 4 fast 21 24 21 23 slow 26 31 26 27 quietio 33 32 33 30 6 fast 15 17 15 16 slow 19 22 19 19 quietio 25 23 25 19 8 fast 12 15 12 14 slow 15 18 15 16 quietio 21 19 21 16 12 fast 1 3 1 1 slow 2 7 2 4 quietio 3 8 3 8 16 fast 1 3 1 1 slow 3 7 3 3 quietio 4 9 4 8 24 fast n/a 3 n/a 1 slow n/a 5 n/a 2 quietio n/a 8 n/a 6 sstl_2_i (3) 10 11 10 11 sstl_2_ii (3) n/a 7 n/a 7 diff_sstl_2_i (3) 30 33 30 33 diff_sstl_2_ii (3) n/a 21 n/a 24 ta bl e 3 3 : sso limit per v cco /gnd pair (cont?d) v cco i/o standard drive slew sso limit per v cco /gnd pair all tqg144, cpg196, csg225, ft(g)256, and lx devices in csg324 all csg484, fg(g)484, fg(g)676, fg(g)900, and lxt devices in csg324 bank 0/2 bank 1/3 bank 0/2 bank 1/3/4/5
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 34 3.3v lvcmos33 2 fast 42 46 42 44 slow 50 55 50 49 quietio 60 68 60 60 4 fast 21 27 21 25 slow 32 37 32 32 quietio 39 42 39 37 6 fast 14 19 14 17 slow 19 25 19 22 quietio 29 30 29 25 8 fast 11 15 11 14 slow 15 20 15 18 quietio 25 24 25 20 12 fast 1 3 1 1 slow 2 5 2 2 quietio 4 9 4 7 16 fast 1 2 1 1 slow 1 5 1 1 quietio 3 10 3 8 24 fast 1 2 1 1 slow 2 5 2 1 quietio 7 9 7 7 ta bl e 3 3 : sso limit per v cco /gnd pair (cont?d) v cco i/o standard drive slew sso limit per v cco /gnd pair all tqg144, cpg196, csg225, ft(g)256, and lx devices in csg324 all csg484, fg(g)484, fg(g)676, fg(g)900, and lxt devices in csg324 bank 0/2 bank 1/3 bank 0/2 bank 1/3/4/5
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 35 3.3v lv t t l 2 fast 53 65 53 62 slow 70 80 70 73 quietio 79 89 79 91 4 fast 23 30 23 27 slow 34 41 34 37 quietio 44 49 44 46 6 fast 16 21 16 20 slow 21 28 21 25 quietio 34 39 34 34 8 fast 12 16 12 15 slow 16 22 16 19 quietio 27 28 27 24 12 fast 1 3 1 1 slow 2 5 2 4 quietio 2 10 2 8 16 fast 1 3 1 1 slow 1 7 1 2 quietio 3 11 3 8 24 fast 1 2 1 1 slow 2 5 2 2 quietio 8 9 8 8 pci33_3 18 19 18 19 pci66_3 18 19 18 19 sstl_3_i 585 8 sstl_3_ii 3 5 3 3 diff_sstl_3_i 15 24 15 24 diff_sstl_3_ii 9 15 9 9 sdio 17 18 17 15 ta bl e 3 3 : sso limit per v cco /gnd pair (cont?d) v cco i/o standard drive slew sso limit per v cco /gnd pair all tqg144, cpg196, csg225, ft(g)256, and lx devices in csg324 all csg484, fg(g)484, fg(g)676, fg(g)900, and lxt devices in csg324 bank 0/2 bank 1/3 bank 0/2 bank 1/3/4/5
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 36 various lvds_33 16 n/a 16 n/a lvds_25 20 n/a 20 n/a blvds_25 20 48 20 20 mini_lvds_33 13 n/a 13 n/a mini_lvds_25 18 n/a 18 n/a rsds_33 12 n/a 12 n/a rsds_25 15 n/a 15 n/a tmds_33 83 n/a 83 n/a ppds_33 12 n/a 12 n/a ppds_25 16 n/a 16 n/a display_port 42 40 42 30 i2c 47 55 47 42 smbus 44 52 44 40 notes: 1. sso limits greater than the number of i/o per v cco /gnd pair ( ta b l e 3 2 ) indicate no limit for the given i/o standard. they are provided in this table to calculate limits when using multiple i/o standards in a bank. 2. not available (n/a) indicates that the i/o standard is not available in the given bank. 3. when used with the mcb, these signals are exempt from sso anal ysis due to the known activity of the mcb switching patterns. s so performance is validated for all mcb instances. mcb outputs can, in some cases, exceed the sso limits. ta bl e 3 3 : sso limit per v cco /gnd pair (cont?d) v cco i/o standard drive slew sso limit per v cco /gnd pair all tqg144, cpg196, csg225, ft(g)256, and lx devices in csg324 all csg484, fg(g)484, fg(g)676, fg(g)900, and lxt devices in csg324 bank 0/2 bank 1/3 bank 0/2 bank 1/3/4/5
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 37 input/output logic switching characteristics ta bl e 3 4 : ilogic2 switching characteristics symbol description speed grade units -3 -3n -2 -1l setup/hold t ice0ck /t ickce0 ce0 pin setup/hold with respect to clk 0.56 ?0.30 0.56 ?0.25 0.79 ?0.22 1.21 ?0.52 ns t isrck /t icksr sr pin setup/hold with respect to clk 0.74 ?0.23 0.74 ?0.22 0.98 ?0.20 1.31 ?0.45 ns t idock /t iockd d pin setup/hold with respect to clk without delay 1.19 ?0.83 1.36 ?0.83 1.73 ?0.83 2.18 ?1.77 ns t idockd /t iockdd ddly pin setup/hold with respect to clk (using iodelay2) 0.31 0.00 0.47 0.00 0.54 0.00 0.63 ?0.39 ns combinatorial t idi d pin to o pin propagation delay, no delay 0.95 1.28 1.53 2.25 ns t idid ddly pin to o pin propagation delay (using iodelay2) 0.23 0.39 0.44 0.74 ns sequential delays t idlo d pin to q pin using flip-flop as a latch without delay 1.56 1.86 2.39 3.49 ns t idlod ddly pin to q1 pin using flip-flop as a latch (using iodelay2) 0.68 0.97 1.20 1.94 ns t ickq clk to q outputs 1.03 1.24 1.43 2.11 ns t rq_ilogic2 sr pin to q outputs 1.81 1.81 2.50 3.05 ns ta bl e 3 5 : ologic2 switching characteristics symbol description speed grade units -3 -3n -2 -1l setup/hold t odck /t ockd d1/d2 pins setup/hold with respect to clk 0.81 ?0.05 0.86 ?0.05 1.18 0.00 1.73 ?0.27 ns t ooceck /t ockoce oce pin setup/hold with respect to clk 0.75 ?0.10 0.75 ?0.10 1.01 ?0.05 1.66 ?0.23 ns t osrck /t ocksr sr pin setup/hold with respect to clk 0.70 ?0.28 0.79 ?0.28 1.03 ?0.23 1.39 ?0.47 ns t otck /t ockt t1/t2 pins setup/hold wi th respect to clk 0.24 ?0.08 0.56 ?0.06 0.83 ?0.01 0.99 ?0.19 ns t otceck /t ocktce tce pin setup/hold with respect to clk 0.58 ?0.06 0.72 ?0.06 1.18 ?0.01 1.51 ?0.13 ns sequential delays t ockq clk to oq/tq out 0.48 0.51 0.74 0.68 ns t rq_ologic2 sr pin to oq/tq out 1.81 1.81 2.50 3.05 ns
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 38 input serializer/deserializer switching characteristics output serializer/deserializ er switching characteristics ta bl e 3 6 : iserdes2 switchi ng characteristics symbol description speed grade units -3 -3n -2 -1l setup/hold for control lines t iscck_bitslip / t isckc_bitslip bitslip pin setup/hold with respect to clkdiv 0.16 ?0.09 0.20 ?0.09 0.31 ?0.09 0.34 ?0.14 ns t iscck_ce / t isckc_ce ce pin setup/hold with respect to clk 0.71 ?0.47 0.71 ?0.42 0.97 ?0.42 1.39 ?0.71 ns setup/hold for data lines t isdck_d /t isckd_d d pin setup/hold with respect to clk 0.24 ?0.15 0.25 ?0.05 0.29 ?0.05 0.09 ?0.05 ns t isdck_ddly /t isckd_ddly ddly pin setup/hold with respect to clk (using iodelay2) ?0.25 0.30 ?0.25 0.42 ?0.25 0.56 ?0.54 0.67 ns t isdck_d_ddr /t isckd_d_ddr d pin setup/hold with respect to clk at ddr mode ?0.03 0.04 ?0.03 0.16 ?0.03 0.18 ?0.05 0.12 ns t isdck_ddly_ddr / t isckd_ddly_ddr d pin setup/hold with respect to clk at ddr mode (using iodelay2) ?0.40 0.48 ?0.40 0.53 ?0.40 0.71 ?0.71 0.86 ns sequential delays t iscko_q clkdiv to out at q pin 1.30 1.44 2.02 2.22 ns f clkdiv clkdiv maximum frequency 270 262.5 250 125 mhz ta bl e 3 7 : oserdes2 switchin g characteristics symbol description speed grade units -3 -3n -2 -1l setup/hold t osdck_d /t osckd_d d input setup/hold with respect to clkdiv ?0.03 1.02 ?0.03 1.17 ?0.03 1.27 ?0.02 0.23 ns t osdck_t /t osckd_t (1) t input setup/hold with respect to clk ?0.05 1.03 ?0.05 1.13 ?0.05 1.23 ?0.05 0.24 ns t oscck_oce /t osckc_oce oce input setup/hold with respect to clk 0.12 ?0.03 0.15 ?0.03 0.24 ?0.03 0.28 ?0.17 ns t oscck_tce /t osckc_tce tce input setup/hold with respect to clk 0.14 ?0.08 0.17 ?0.08 0.27 ?0.08 0.31 ?0.16 ns sequential delays t oscko_oq clock to out from clk to oq 0.94 1.11 1.51 1.89 ns t oscko_tq clock to out from clk to tq 0.94 1.11 1.51 1.91 ns f clkdiv clkdiv maximum frequency 270 262.5 250 125 mhz notes: 1. t osdck_t2 /t osckd_t2 (t input setup/hold with respec t to clkdiv) are reported as t osdck_t /t osckd_t in trace report.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 39 input/output delay swit ching characteristics ta bl e 3 8 : iodelay2 switching characteristics symbol description speed grade units -3 -3n -2 -1l t iodcck_cal / t iodckc_cal cal pin setup/hold with respect to ck 0.28 ?0.13 0.33 ?0.13 0.48 ?0.13 ?ns t iodcck_ce / t iodckc_ce ce pin setup/hold with respect to ck 0.17 ?0.03 0.17 ?0.03 0.25 ?0.02 ?ns t iodcck_inc / t iodckc_inc inc pin setup/hold with respect to ck 0.10 0.02 0.12 0.03 0.18 0.06 ?ns t iodcck_rst / t iodckc_rst rst pin setup/hold with respect to ck 0.12 ?0.02 0.15 ?0.02 0.22 ?0.01 ?ns t tap1 (2) maximum tap 1 delay 8 14 16 ? ps t tap2 maximum tap 2 delay 40 66 77 ? ps t tap3 maximum tap 3 delay 95 120 140 ? ps t tap4 maximum tap 4 delay 108 141 166 ? ps t tap5 maximum tap 5 delay 171 194 231 ? ps t tap6 maximum tap 6 delay 207 249 292 ? ps t tap7 maximum tap 7 delay 212 276 343 ? ps t tap8 maximum tap 8 delay 322 341 424 ? ps f mincal minimum allowed bit rate for calibration in variable mode: variable_from_zero, variable_from_half_max, and diff_phase_detector. 188 188 188 ? mb/s t ioddo_idatain propagation delay through iodelay2 note 1 note 1 note 1 note 3 ? t ioddo_odatain propagation delay through iodelay2 note 1 note 1 note 1 note 3 ? notes: 1. delay depends on iodelay2 tap setting. see trace report for actual values. 2. maximum delay = integer (number of taps/8) ? t ta p 8 +t ta p n (where n equals the remainder). for minimum delay consult the trace setup and hold report. minimum delay is greater than 30% of the maximum delay. tap delays can vary by device. see trace report for ac tual values. 3. spartan-6 -1l devices only support tap 0.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 40 clb switching characteristics (slicem only) ta bl e 3 9 : clb switching characteristics (slicem only) symbol description speed grade units -3 -3n -2 -1l combinatorial delays t ilo an ? dn lut inputs to a to d outputs 0.21 0.26 0.26 0.46 ns, max an ? dn lut inputs through f7amux/f7bmux to amux/cmux output 0.37 0.43 0.43 0.77 ns, max t opab an ? dn lut inputs through f7amux or f7bmux and f8mux to bmux output 0.37 0.46 0.46 0.84 ns, max t ito an ? dn lut inputs through latch to aq ? dq outputs 0.82 0.95 0.95 1.64 ns, max t tito_logic an ? dn lut inputs to aq ? dq outputs (latch as logic) 0.82 0.95 0.95 1.64 ns, max t opcya an lut inputs to cout output 0.38 0.48 0.48 0.69 ns, max t opcyb bn lut inputs to cout output 0.38 0.49 0.49 0.71 ns, max t opcyc cn lut inputs to cout output 0.28 0.33 0.33 0.55 ns, max t opcyd dn lut inputs to cout output 0.28 0.35 0.35 0.52 ns, max t axcy ax input to cout output 0.21 0.26 0.26 0.36 ns, max t bxcy bx input to cout output 0.13 0.16 0.16 0.18 ns, max t cxcy cx input to cout output 0.10 0.12 0.12 0.09 ns, max t dxcy dx input to cout output 0.09 0.11 0.11 0.09 ns, max t byp cin input to cout output 0.08 0.10 0.10 0.06 ns, max t cina cin input to amux output 0.21 0.22 0.22 0.47 ns, max t cinb cin input to bmux output 0.30 0.31 0.31 0.57 ns, max t cinc cin input to cmux output 0.29 0.31 0.31 0.58 ns, max t cind cin input to dmux output 0.31 0.32 0.32 0.68 ns, max sequential delays t cko clock to aq ? dq outputs 0.45 0.53 0.53 0.74 ns, max setup and hold times of clb fl ip-flops before/after clock clk t dick /t ckdi ax ? dx input to clk on a ? d flip-flops 0.42 0.28 0.47 0.39 0.47 0.39 0.90 0.56 ns, min t ceck /t ckce ce input to clk on a ? d flip-flops 0.31 ?0.07 0.37 ?0.07 0.37 ?0.07 0.59 ?0.27 ns, min t srck /t cksr sr input to clk on a ? d flip-flops 0.41 0.02 0.42 0.02 0.42 0.02 0.68 ?0.29 ns, min t cinck /t ckcin cin input to clk on a ? d flip-flops 0.31 ?0.17 0.31 ?0.13 0.31 ?0.13 0.81 ?0.42 ns, min set/reset t rpw sr input minimum pulse width 0.41 0.48 0.48 1.37 ns, min t rq delay from sr input to aq ? dq flip-flops 0.60 0.70 0.70 3.05 ns, max t ceo delay from ce input to aq ? dq flip-flops 0.60 0.65 0.65 0.90 ns, max f tog toggle frequency (for export control) 862 806 667 500 mhz
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 41 clb distributed ram switching characteristics (slicem only) clb shift register switching characteristics (slicem only) ta bl e 4 0 : clb distributed ram switching characteristics (slicem only) symbol description speed grade units -3 -3n -2 -1l sequential delays t shcko clock to a ? d outputs 1.26 1.55 1.55 2.35 ns, max clock to a ? d outputs (direct output path) 0.96 1.20 1.20 1.87 ns, max setup and hold times before/after clock clk t ds /t dh ax ? dx or ai ? di inputs to clk 0.59 0.17 0.73 0.22 0.73 0.22 1.17 0.33 ns, min t as /t ah address an inputs to clock 0.28 0.35 0.32 0.42 0.32 0.42 0.26 0.71 ns, min t ws /t wh we input to clock 0.31 ?0.08 0.37 ?0.08 0.37 ?0.08 0.59 ?0.27 ns, min t ceck /t ckce ce input to clk 0.31 ?0.08 0.37 ?0.08 0.37 ?0.08 0.59 ?0.27 ns, min ta bl e 4 1 : clb shift register switching characteristics symbol description speed grade units -3 -3n -2 -1l sequential delays t reg clock to a ? d outputs 1.35 1.78 1.78 2.74 ns, max clock to a ? d outputs (direct output path) 1.24 1.65 1.65 2.48 ns, max setup and hold times before/after clock clk t ws /t wh we input to clk 0.20 ?0.07 0.24 ?0.07 0.24 ?0.07 0.29 ?0.27 ns, min t ceck /t ckce ce input to clk 0.29 0.36 0.29 0.38 0.29 0.38 0.82 ?0.41 ns, min t ds /t dh ax ? dx or ai ? di inputs to clk 0.07 0.11 0.09 0.14 0.09 0.14 0.11 0.23 ns, min
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 42 block ram switching characteristics ta bl e 4 2 : block ram switching characteristics symbol description speed grade units -3 -3n -2 -1l block ram clock to out delays t rcko_do clock clk to dout output (without output register) (1) 1.85 2.10 2.10 3.50 ns, max t rcko_do_reg clock clk to dout output (with output register) (2) 1.60 1.75 1.75 2.30 ns, max setup and hold times before/after clock clk t rcck_addr /t rckc_addr addr inputs (3) 0.35 0.10 0.40 0.12 0.40 0.12 0.50 0.15 ns, min t rdck_di /t rckd_di din inputs (4) 0.30 0.10 0.30 0.10 0.30 0.10 0.40 0.15 ns, min t rcck_en /t rckc_en block ram enable (en) input 0.22 0.05 0.22 0.06 0.22 0.06 0.44 0.10 ns, min t rcck_regce /t rckc_regce ce input of out put register 0.20 0.10 0.20 0.10 0.20 0.10 0.28 0.15 ns, min t rcck_we /t rckc_we write enable (we) input 0.25 0.10 0.33 0.10 0.33 0.10 0.28 0.15 ns, min maximum frequency f max block ram in all modes 320 280 260 150 mhz notes: 1. t rcko_do includes t rcko_doa and t rcko_dopa as well as the b port equi valent timing parameters. 2. t rcko_do_reg includes t rcko_doa_reg and t rcko_dopa_reg as well as the b port equi valent timing parameters. 3. the addr setup and hold must be met when en is asserted (eve n when we is deasserted). otherwise, block ram data corruption is possible. 4. t rdck_di includes both a and b inputs as well as the parity inputs of a and b.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 43 dsp48a1 switching characteristics ta bl e 4 3 : dsp48a1 switching characteristics symbol description pre- adder multiplier post- adder speed grade units -3 -3n -2 -1l setup and hold times of data/control pins to the input register clock t dspdck_a_a1reg / t dspckd_a_a1reg a input to a1 register clk n/a n/a n/a 0.15 0.09 0.17 0.09 0.17 0.09 0.32 0.09 ns t dspdck_d_b1reg / t dspckd_d_b1reg d input to b1 register clk yes n/a n/a 1.90 ?0.07 1.95 ?0.07 1.95 ?0.07 2.82 ?0.07 ns t dspdck_c_creg / t dspckd_c_creg c input to c register clk n/a n/a n/a 0.11 0.15 0.13 0.15 0.13 0.15 0.24 0.09 ns t dspdck_d_dreg / t dspckd_d_dreg d input to d register clk n/a n/a n/a 0.09 0.15 0.10 0.15 0.10 0.15 0.19 0.12 ns t dspdck_opmode_b1reg / t dspckd_opmode_b1reg opmode input to b1 register clk yes n/a n/a 1.97 0.01 2.00 0.01 2.00 0.01 2.85 0.01 ns t dspdck_opmode_opmodereg / t dspckd_opmode_opmodereg opmode input to opmode register clk n/a n/a n/a 0.18 0.12 0.21 0.12 0.21 0.12 0.40 0.12 ns setup and hold times of data pins to the pipeline register clock t dspdck_a_mreg / t dspckd_a_mreg a input to m register clk n/a yes n/a 3.06 ?0.40 3.51 ?0.40 3.51 ?0.40 3.97 ?0.40 ns t dspdck_b_mreg / t dspckd_b_mreg b input to m register clk yes yes n/a 3.96 ?0.68 4.58 ?0.68 4.58 ?0.68 7.00 ?0.68 ns t dspdck_d_mreg / t dspckd_d_mreg d input to m register clk yes yes n/a 4.23 ?0.56 4.80 ?0.56 4.80 ?0.56 6.84 ?0.56 ns t dspdck_opmode_mreg / t dspckd_opmode_mreg opmode to m register clk yes yes n/a 4.18 ?0.48 4.80 ?0.48 4.80 ?0.48 6.88 ?0.48 ns no yes n/a 2.37 ?0.48 2.70 ?0.48 2.70 ?0.48 4.28 ?0.48 ns setup and hold times of data/control pins to the output register clock t dspdck_a_preg / t dspckd_a_preg a input to p register clk n/a yes yes 4.32 ?0.76 5.06 ?0.76 5.06 ?0.76 7.52 ?0.76 ns t dspdck_b_preg / t dspckd_b_preg b input to p register clk yes yes yes 5.87 ?0.59 6.87 ?0.59 6.87 ?0.59 10.55 ?0.59 ns no yes yes 4.14 ?0.93 4.68 ?0.93 4.68 ?0.93 8.12 ?0.93 ns t dspdck_c_preg / t dspckd_c_preg c input to p register clk n/a n/a yes 2.20 ?0.23 2.25 ?0.23 2.25 ?0.23 3.27 ?0.23 ns t dspdck_d_preg / t dspckd_d_preg d input to p register clk yes yes yes 5.90 ?0.92 6.91 ?0.92 6.91 ?0.92 10.39 ?0.92 ns t dspdck_opmode_preg / t dspckd_opmode_preg opmode input to p regi ster clk yes yes yes 6.21 ?0.84 7.27 ?0.84 7.27 ?0.84 10.43 ?0.84 ns no yes yes 1.69 ?0.87 1.98 ?0.87 1.98 ?0.87 3.62 ?0.87 ns no no yes 2.09 ?0.22 2.30 ?0.22 2.30 ?0.22 3.79 ?0.22 ns
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 44 clock to out from output re gister clock to output pin t dspcko_p_preg clk (preg) to p output n/a n/a n/a 1.20 1.34 1.34 1.90 ns clock to out from pipeline register clock to output pins t dspcko_p_mreg clk (mreg) to p output n/a n/a yes 3.38 3.95 3.95 5.83 ns clock to out from input regi ster clock to output pins t dspcko_p_a1reg clk (a1reg) to p output n/a yes yes 5.02 5.87 5.87 9.65 ns t dspcko_p_b1reg clk (b1reg) to p output n/a yes yes 5.02 5.87 5.87 9.63 ns t dspcko_p_creg clk (creg) to p output n/a n/a yes 3.12 3.64 3.64 5.24 ns t dspcko_p_dreg clk (dreg) to p output yes yes yes 6.77 7.92 7.92 12.53 ns combinatorial delays from input pins to output pins t dspdo_a_p a input to p output n/a no yes 2.85 3.33 3.33 4.73 ns n/a yes no (2) 3.35 3.93 3.93 6.74 ns n/a yes yes 4.56 5.22 5.22 8.94 ns t dspdo_b_p b input to p output yes no no (2) 3.22 3.76 3.76 5.55 ns ye s ye s n o (2) 6.01 6.54 6.54 9.76 ns yes yes yes 6.27 7.34 7.34 11.96 ns t dspdo_c_p c input to p output n/a n/a yes 2.69 3.15 3.15 4.68 ns t dspdo_d_p d input to p output yes yes yes 6.31 7.38 7.38 11.81 ns t dspdo_opmode_p opmode input to p output yes yes yes 6.43 7.52 7.52 11.84 ns no yes yes 4.84 5.66 5.66 9.25 ns no no yes 3.11 3.49 3.49 5.03 ns maximum frequency f max all registers used yes yes yes 390 333 333 213 mhz notes: 1. a yes signifies that the component is in the path. a no signifies that the component is being bypassed. n/a signifies not app licable because no path exists. 2. implemented in the post-adder by adding to zero. ta bl e 4 3 : dsp48a1 switching characteristics (cont?d) symbol description pre- adder multiplier post- adder speed grade units -3 -3n -2 -1l
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 45 ta bl e 4 4 : device dna interface port switching characteristics symbol description speed grade units -3 -3n -2 -1l t dnassu setup time on shift before the rising edge of clk 7 ns, min t dnash hold time on shift after the rising edge of clk 1 ns, min t dnadsu setup time on din before the rising edge of clk 7 ns, min t dnadh hold time on din after the rising edge of clk 1 ns, min t dnarsu setup time on read before the rising edge of clk 7ns, min 1,000 ns, max t dnarh hold time on read after the rising edge of clk 1 ns, min t dnadcko clock-to-output delay on dout after rising edge of clk 0.5 ns, min 6ns, max t dnaclkf (2) clk frequency 2 mhz, max t dnaclkl clk low time 50 ns, min t dnaclkh clk high time 50 ns, min notes: 1. the minimum read pulse width is 8 ns, the maximum read pulse width is 1 s. 2. also applies to tck when reading dna through the boundary-scan port. ta bl e 4 5 : suspend mode switching characteristics symbol description min max units entering suspend mode t suspendhigh_awake rising edge of suspend pin to falling edge of awake pin wi thout glitch filter 2.5 14 ns t suspendfilter adjustment to suspend pin rising edge param eters when glitch filter enabled 31 430 ns t suspend_gwe rising edge of suspend pin until fp ga output pins drive their defined suspend constraint behavior (without glitch filter) ?15ns t suspend_gts rising edge of suspend pin to write-pr otect lock on all writable clocked elements (without glitch filter) ?15ns t suspend_disable rising edge of the suspend pin to fpga input pins and interconnect disabled (without glitch filter) ? 1500 ns exiting suspend mode t suspendlow_awake falling edge of the suspend pin to rising edge of the awake pin. does not include dcm or pll lock time. 775s t suspend_enable falling edge of the suspend pin to fpga input pins and interconnect re- enabled 741s t awake_gwe1 rising edge of the awake pin until write-protect lock released on all writable clocked elements, using sw_clk:internalclock and sw_gwe_cycle:1 . ?80ns t awake_gwe512 rising edge of the awake pin until write-protect lock released on all writable clocked elements, using sw_clk:internalclock and sw_gwe_cycle:512 . ?20.5s t awake_gts1 rising edge of the awake pin until outputs return to the behavior described in the fpga application, using sw_clk:internalclock and sw_gts_cycle:1 . ?80ns t awake_gts512 rising edge of the awake pin until outputs return to the behavior described in the fpga application, using sw_clk:internalclock and sw_gts_cycle:512 . ?20.5s t scp_awake rising edge of scp pins to rising edge of awake pin 7 75 s
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 46 configuration switching characteristics ta bl e 4 6 : configuration switching characteristics (1) symbol description speed grade units -3 -3n -2 -1l power-up timing characteristics t pl (2) program_b latency 4 4 4 5 ms, max t por (2) power-on-reset 5/40 5/40 5/40 5/40 ms, min/max t program program_b pulse width 500 500 500 500 ns, min slave serial mode pr ogramming switching t dcck /t cckd din setup/hold, slave mode 6.0/1.0 6.0/1.0 6.0/1.0 8.0/2.0 ns, min t cco cclk to dout 12 12 12 17 ns, max f scck slave mode external cclk 80 80 80 50 mhz, max slave selectmap mode programming switching t smdcck /t smcckd selectmap data setup/hold 6.0/1. 0 6.0/1.0 6.0/1.0 8.0/2.0 ns, min t smcscck /t smcckcs csi_b setup/hold 7.0/0.0 7.0/0.0 7.0/0.0 9.0/2.0 ns, min t smwcck /t smcckw rdwr_b setup/hold 17. 0/1.0 17.0/1.0 17.0/1.0 27.0/2.0 ns, min t smckcso cso_b clock to out 16 16 16 26 ns, max t smco cclk to data out in readback 13 13 13 25 ns, max t smckby cclk to busy out in readback 12 12 12 17 ns, max f smcck maximum cclk frequency (xc6slx4, xc6slx9, xc6slx16, xc6slx25, xc6slx25t, xc6slx45, xc6slx45t, xc6slx75, and xc6slx75t only) 50 50 50 25 mhz, max maximum cclk frequency (xc6slx100 and xc6slx100t in x8 mode, xc6slx150, and xc6slx150t only) 40 40 40 20 mhz, max maximum cclk frequency (xc6slx100 and xc6slx100t in x16 mode only) 35 35 35 20 mhz, max f rbcck maximum readback cclk frequency (xc6slx4, xc6slx9, xc6slx16, xc6slx25, xc6slx25t, xc6slx45, xc6slx45t, xc6slx75, and xc6slx75t only) 20 20 20 4 mhz, max maximum readback cclk frequency (xc6slx100, xc6slx100t, xc6slx150, and xc6slx150t only) 12 12 12 4 mhz, max boundary-scan port timing specifications t taptck tms and tdi setup time before tck 10 10 10 17 ns, min t tcktap tms and tdi hold time after tck 5.5 5.5 5.5 5.5 ns, min t tcktdo tck falling edge to tdo output valid 6.5 6.5 6.5 8 ns, max t tckh tck clock minimum high time 12 12 12 21 ns, min t tckl tck clock minimum low time 12 12 12 21 ns, min f tck maximum configuration tck clock frequency 33 33 33 18 mhz, max f tckb maximum boundary-scan tck clock frequency 33 33 33 18 mhz, max f tckaes maximum aes key tck clock frequency 2 2 2 2 mhz, max bpi master flash mode programming switching (3) t bpicco (4) a[25:0], fcs_b, foe_b, fwe_b, ldc outputs valid after cclk falling edge 15 15 15 20 ns, max t bpiicck master bpi cclk (output) delay 10/ 100 10/100 10/100 10/130 s, min/max
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 47 t bpidcc /t bpiccd setup/hold on d[15:0] data input pins 5.0/1.0 5.0/1.0 5.0/1.0 6.0/2.0 ns, min spi master flash mode programming switching t spidcc /t spidccd din, miso0, miso1, miso 2, miso3, setup/hold before/after the rising cclk edge 5.0/1.0 5.0/1.0 5.0/1.0 7.0/1.0 ns, min t spiicck master spi cclk (output) delay 0.4/7 .0 0.4/7.0 0.4/7.0 0.4/10.0 s, min/max t spiccm mosi clock to out 13 13 13 19 ns, max t spiccfc cso_b clock to out 16 16 16 26 ns, max cclk output (master modes) t mcckl master cclk clock duty cycle low 40/60 %, min/max t mcckh master cclk clock duty cycle high 40/60 %, min/max f mcck maximum frequency, serial mode (master serial/spi) all devices 40 40 40 30 mhz, max maximum frequency, parallel mode (master selectmap/bpi) xc6slx4, xc6slx9, xc6slx16, xc6slx25, xc6slx25t, xc6slx45, xc6slx45t, xc6slx75, and xc6slx75t 40 40 40 25 mhz, max maximum frequency, parallel mode (master selectmap/bpi) xc6slx100 and xc6slx100t in x8 mode, xc6slx150, and xc6slx150t 40 40 40 20 mhz, max maximum frequency, parallel mode (master selectmap/bpi) xc6slx100 and xc6slx100t in x16 mode 35 35 35 20 mhz, max f mccktol frequency tolerance, master mode 50 50 50 50 % cclk input (slave modes) t scckl slave cclk clock minimum low time 5 5 5 8 ns, min t scckh slave cclk clock minimum high time 5 5 5 8 ns, min usercclk input t usercclkl usercclk clock minimum low time 12 12 12 16 ns, min t usercclkh usercclk clock minimum high time 12 12 12 16 ns, min f usercclk maximum usercclk frequency 40 40 40 30 mhz, max notes: 1. maximum frequency and setup/hold timing parameters are for 3.3v and 2.5v configuration voltages. 2. to support longer delays in configuration, use the design solutions described in the spartan-6 fpga configuration user guide . 3. bpi mode is not supported in: ? lx4, lx25, or lx25t devices ? lx9 devices in the tqg144 package ? lx9 or lx16 devices in the cpg196 package. 4. only during configuration, the last edge is determi ned by a weak pull-up/pull-down resistor in the i/o. ta bl e 4 6 : configuration switching characteristics (1) (cont?d) symbol description speed grade units -3 -3n -2 -1l
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 48 clock buffers and networks ta bl e 4 7 : global clock switching characteristics symbol description devices speed grade units -3 -3n -2 -1l t gsi s pin setup to i0/i1 inputs l x family 0.25 0.31 0.48 0.48 ns lxt family 0.25 0.31 0.48 n/a ns t gio bufgmux delay from i0/i1 to o lx family 0.21 0.21 0.21 0.21 ns lxt family 0.21 0.21 0.21 n/a ns maximum frequency f max global clock tree (bufg) lx family 400 400 375 250 mhz lxt family 400 400 375 n/a mhz ta bl e 4 8 : input/output clock switching characteristics (bufio2) symbol description devices speed grade units -3 -3n -2 -1l t bufcko_o clock to out delay from i to o lx family 0.67 0.82 1.09 1.50 ns lxt family 0.67 0.82 1.09 n/a ns maximum frequency f max i/o clock tree (bufio2) lx family 540 525 500 300 mhz lxt family 540 525 500 n/a mhz ta bl e 4 9 : input/output clock switching characteristics (bufpll) symbol description devices speed grade units -3 -3n -2 -1l maximum frequency f max bufpll clock tree (bufpll) lx family 1080 1050 950 500 mhz lxt family 1080 1050 950 n/a mhz
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 49 pll switching characteristics ta bl e 5 0 : pll specification symbol description device (1) speed grade units -3 -3n -2 -1l f inmax maximum input clock frequency from i/o clock lx family 540 525 450 300 mhz lxt family 540 525 450 n/a mhz maximum input clock frequency from global clock lx family 400 400 375 250 mhz lxt family 400 400 375 n/a mhz f inmin minimum input clock frequency lx family 19 19 19 19 mhz lxt family 19 19 19 n/a mhz f injitter maximum input clock period jitter all <20% of clock input period or 1 ns max f induty allowable input duty cycle: 19?199 mhz all 25/75 % allowable input duty cycle: 200?299 mhz all 35/65 % allowable input duty cycle: > 300 mhz all 45/55 % f vcomin minimum pll vco frequency lx family 400 400 400 400 mhz lxt family 400 400 400 n/a mhz f vcomax maximum pll vco frequency lx family 1080 1050 1000 1000 mhz lxt family 1080 1050 1000 n/a mhz f bandwidth low pll bandwidth at typical (3) all 1 1 1 1 mhz high pll bandwidth at typical (3) all 4 4 4 4 mhz t staphaoffset static phase offset of the pl l outputs all 0.12 0.12 0.12 0.15 ns t outjitter pll output jitter (3) all note 2 t outduty pll output clock duty cycle precision (4) all 0.15 0.15 0.20 0.25 ns t lockmax pll maximum lock time all 100 100 100 100 s f outmax pll maximum output frequency for bufgmux lx family 400 400 375 250 mhz lxt family 400 400 375 n/a mhz f outmax pll maximum output frequency for bufpll lx family 1080 1050 950 500 mhz lxt family 1080 1050 950 n/a mhz f outmin pll minimum output frequency (5) all 3.125 3.125 3.125 3.125 mhz t extfdvar external clock feedback variation all < 20% of clock input period or 1 ns max rst minpulse minimum reset pulse width all 5 5 5 5 ns f pfdmax (5) maximum frequency at the phase frequency detector lx family 500 500 400 300 mhz lxt family 500 500 400 n/a mhz f pfdmin minimum frequency at the phase frequency detector lx family 19 19 19 19 mhz lxt family 19 19 19 n/a mhz t fbdelay maximum delay in the feedback path all 3 ns max or one clkin cycle notes: 1. lxt devices are not available with a -1l speed grade. 2. values for this parameter are available in the clocking wizard. 3. the pll does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequenc ies. 4. includes global clock buffer. 5. calculated as f vco /128 assuming output duty cycle is 50%. 6. when using clk_feedback = clkout0 with bufio2 feedback, the feedback frequency will be higher than the phase frequency detector frequency. f pfdmax = f clkfb / clkfbout_mult
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 50 dcm switching characteristics ta bl e 5 1 : operating frequency ranges and conditions for the delay-locked loop (dll) (1) symbol description speed grade units -3 -3n -2 -1l minmaxminmaxminmaxminmax input frequency ranges clkin_freq_dll frequency of the clkin clock input when the clkdv output is not used. 5 (2) 280 (3) 5 (2) 280 (3) 5 (2) 250 (3) 5 (2) 175 (3) mhz frequency of the clkin clock input when using the clkdv output. 5 (2) 280 (3) 5 (2) 280 (3) 5 (2) 250 (3) 5 (2) 133 (3) mhz input pulse requirements clkin_pulse clkin pulse width as a percentage of the clkin period for clkin_freq_dll < 150 mhz 40 60 40 60 40 60 40 60 % clkin pulse width as a percentage of the clkin period for clkin_freq_dll > 150 mhz 45 55 45 55 45 55 45 55 % input clock jitter tolerance and delay path variation (4) clkin_cyc_jitt_dll_lf cycle-to-cycle jitter at the clkin input for clkin_freq_dll < 150 mhz ? 300 ? 300 ? 300 ? 300 ps clkin_cyc_jitt_dll_hf cycle-to-cycle jitte r at the clkin input for clkin_freq_dll > 150 mhz. ? 150 ? 150 ? 150 ? 150 ps clkin_per_jitt_dll period jitter at the clkin input. ? 1 ? 1 ? 1 ? 1 ns clkfb_delay_var_ext allowable variation of the off-chip feedback delay from the dcm output to the clkfb input. ?1?1?1?1ns notes: 1. dll specifications apply when using any of the dll outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, or clkdv. 2. when operating independently of the dll, the dfs supports lower clkin_freq_dll frequencies. see ta b l e 5 3 . 3. the clkin_divide_by_2 attribute increases the effective i nput frequency range. when set to true, the input clock frequency is divided by two as it enters the dcm. input clock frequencies for the cl ock buffer being used can be increased up to the f max (see ta bl e 4 7 and ta b l e 4 8 for bufg and bufio2 limits). when used with clk_feedback=2x, the input cl ock frequency matches the frequency for clk2x, and is limited to clkout_freq_2x. 4. clkin_freq_dll input jitter beyond these limits can cause the dcm to lose lock, indicated by the locked output deasserting. t he user must then reset the dcm. 5. when using both dcms in a cmt, both dcms must be locked.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 51 ta bl e 5 2 : switching characteristics for the delay-locked loop (dll) (1) symbol description speed grade units -3 -3n -2 -1l min max min max min max min max output frequency ranges clkout_freq_clk0 frequency for the clk0 and clk180 outputs. 5 280 5 280 5 250 5 175 mhz clkout_freq_clk90 frequency for the clk90 and clk270 outputs. 5 200 5 200 5 200 5 175 mhz clkout_freq_2x frequency for the clk2x and clk2x180 outputs. 10 375 10 375 10 334 10 250 mhz clkout_freq_dv frequency for the clkdv output. 0.3125 186 0.3125 186 0.3125 166 0.3125 88.6 mhz output clock jitter (2)(3)(4) clkout_per_jitt_0 period jitter at t he clk0 output. ? 100 ? 100 ? 100 ? 100 ps clkout_per_jitt_90 period jitter at t he clk90 output. ? 150 ? 150 ? 150 ? 150 ps clkout_per_jitt_180 period jitter at t he clk180 output. ? 150 ? 150 ? 150 ? 150 ps clkout_per_jitt_270 period jitter at t he clk270 output. ? 150 ? 150 ? 150 ? 150 ps clkout_per_jitt_2x period jitter at the clk2x and clk2x180 outputs. maximum = [0.5% of clkin period + 100] ps clkout_per_jitt_dv1 period ji tter at the clkdv output when performing integer division. ? 150 ? 150 ? 150 ? 150 ps clkout_per_jitt_dv2 period ji tter at the clkdv output when performing non-integer division. maximum = [0.5% of clkin period + 100] ps duty cycle (4) clkout_duty_cycle_ dll duty cycle variation for the clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv outputs, including the bufgmux and clock tree duty-cycle distortion. typical = [1% of clkin period + 350] ps phase alignment (4) clkin_clkfb_phase phase offset between the clkin and clkfb inputs (clk_feedback = 1x). ? 150 ? 150 ? 150 ? 250 ps max phase offset between the clkin and clkfb inputs (clk_feedback = 2x). ? 250 ? 250 ? 250 ? 350 clkout_phase_dll phase offset between dll outputs for clk0 to clk2x (not clk2x180). maximum = [1% of clkin period + 100] ps phase offset between dll outputs for all others. maximum = [1% of clkin period + 150] maximum = [1% of clkin period + 200] ps
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 52 lock_dll (3) when using the dll alone: the time from deassertion at the dcm?s reset input to the rising transition at its locked output. when the dcm is locked, the clkin and clkfb signals are in phase. 5 mhz < clkin_freq_dll <50mhz. ?5?5?5?5ms when using the dll alone: the time from deassertion at the dcm?s reset input to the rising transition at its locked output. when the dcm is locked, the clkin and clkfb signals are in phase. clkin_freq_dll > 50 mhz ? 0.60 ? 0.60 ? 0.60 ? 0.60 ms delay lines dcm_delay_step (5) finest delay resolution, averaged over all steps. 10 40 10 40 10 40 10 40 ps notes: 1. the values in this table are based on the operating conditions described in ta b l e 2 and ta b l e 5 1 . 2. indicates the maximum amount of output jitter that the dcm adds to the jitter on the clkin input. 3. for optimal jitter tolerance and faster lock time, use the clkin_period attribute. 4. some jitter and duty-cycle specifications include 1% of input cl ock period or 0.01 ui. for example, this data sheet specifies a maximum jitter of (1% of clkin period + 150 ps). assuming that the clkin frequency is 10 0 mhz, the equivalent clkin period is 10 ns. since 1% of 10 ns i s 0.1 ns or 100 ps, the maximum jitter is (100 ps + 150 ps) = 250 ps. 5. a typical delay step size is 23 ps. ta bl e 5 3 : recommended operating conditions for th e digital frequency synthesizer (dfs) (1) symbol description speed grade units -3 -3n -2 -1l min max min max min max min max input frequency ranges (2) clkin_freq_fx frequency for the clkin input. also described as f clkin . 0.5 375 (3) 0.5 375 (3) 0.5 333 (3) 0.5 200 (3) mhz input clock jitter tolerance (4) clkin_cyc_jitt_f x_lf cycle-to-cycle jitter at the clkin input, based on clkfx output frequency: fclkfx < 150 mhz. ?300?300?300?300ps clkin_cyc_jitt_fx_hf c ycle-to-cycle jitter at the clkin input, based on clkfx output frequency: fclkfx > 150 mhz. ?150?150?150?150ps clkin_per_jitt_fx period jitter at the clkin input. ? 1 ? 1 ? 1 ? 1 ns notes: 1. dfs specifications apply w hen using either of the dfs outputs (clkfx or clkfx180). 2. when using both dfs and dll outputs on the same dcm, follo w the more restrictive clkin_freq_dll specifications in ta b l e 5 1 . 3. the clkin_divide_by_2 attribute increases the effective input frequency range. when set to true, the input clock frequency is divided by two as it enters the dcm. input clock frequencies for the clock buffer being used can be increased up to the f max (see ta bl e 4 7 and ta bl e 4 8 for bufg and bufio2 limits). 4. clkin input jitter beyond these limi ts can cause the dcm to lose lock. ta bl e 5 2 : switching characteristics for the delay-locked loop (dll) (1) (cont?d) symbol description speed grade units -3 -3n -2 -1l min max min max min max min max
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 53 ta bl e 5 4 : switching characteristics for the digital frequency synthesizer (dfs) for dcm_sp (1) symbol description speed grade units -3 -3n -2 -1l min max min max min max min max output frequency ranges clkout_freq_fx frequency for the clkfx and clkfx180 outputs 5375537553335200mhz output clock jitter (2)(3) clkout_per_jitt_fx period jitter at the clkfx and clkfx180 outputs. when clkin < 20 mhz use the clocking wizard ps period jitter at the clkfx and clkfx180 outputs. when clkin > 20 mhz typical = (1% of clkfx period + 100) ps duty cycle (4)(5) clkout_duty_cycle_fx duty cycle precision for the clkfx and clkfx180 outputs including the bufgmux and clock tree duty-cycle distortion maximum = (1% of clkfx period + 350) ps phase alignment (5) clkout_phase_fx phase offset between the dfs clkfx output and the dll clk0 output when both the dfs and dll are used ? 200 ? 200 ? 200 ? 250 ps clkout_phase_fx180 phase offset between the dfs clkfx180 output and the dll clk0 output when both the dfs and dll are used maximum = (1% of clkfx period + 200) ps locked time lock_fx (2) when 5 mhz < fclkin < 50 mhz, the time from deassertion at the dcm?s reset input to the rising transition at its locked output. the dfs asserts locked when the clkfx and clkfx180 signals are valid. when using both the dll and the dfs, use the longer locking time. ?5?5?5?5ms when fclkin > 50 mhz, the time from deassertion at the dcm?s reset input to the rising transition at its locked output. the dfs asserts locked when the clkfx and clkfx180 signals are valid. when using both the dll and the dfs, use the longer locking time. ?0.45?0.45?0.45?0.60ms notes: 1. the values in this table are based on the operating conditions described in ta b l e 2 and ta b l e 5 3 . 2. for optimal jitter tolerance and a faster lock time, use the clkin_period attribute. 3. output jitter is characterized with no input jitter. output jitter strongly depends on the en vironment, including the number of ssos, the output drive strength, clb utilization, clb switching activities, switching frequency, power supply, and pcb design. the actual maximum outp ut jitter depends on the system application. 4. the clkfx, clkfxdv, and clkfx180 outputs have a duty cycle of approximately 50%. 5. some duty cycle and alignment s pecifications include a percentage of the clkfx output period. for example, this data sheet sp ecifies a maximum clkfx jitter of (1% of clkfx period + 200 ps). assuming that the cl kfx output frequency is 100 mhz, the equivalent clkfx period is 10 ns, and 1% of 10 ns is 0.1 ns or 100 ps. accordingly, the maximum jitter is (100 ps + 200 ps) = 300 ps.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 54 ta bl e 5 5 : switching characteristics for the digital frequency synthesizer dfs (dcm_clkgen) (1) symbol description speed grade units -3 -3n -2 -1l min max min max min max min max output frequency ranges (dcm_clkgen) clkout_freq_fx frequency for the clkfx and clkfx180 outputs 5375537553335200mhz clkout_freq_fxdv frequency for the clkfxdv output 0.15625 187.5 0.15625 187.5 0.15625 166.5 0.15625 100 mhz output clock jitter (2)(3) clkout_per_jitt_fx period jitter at the clkfx and clkfx180 outputs. typical = [0.2% of clkfx period + 100] ps clkout_per_jitt_fxdv period jitter at the clkfxdv output. typical = [0.2% of clkfx period + 100] ps clkfx_freeze_var clkfx period change in free running oscillator mode at the same temperature. fclkfx > 50 mhz maximum = 3% of clkfx period ps clkfx period change in free running oscillator mode at the same temperature. fclkfx < 50 mhz maximum = 5% of clkfx period ps clkfx_freeze_temp _slope clkfx period will change in free_oscillator mode over temperature. add to clkfx_freeze_var to determine total clkfx period change. percentage change for clkfx period over 1c. maximum = 0.1 %/c duty cycle (4)(5) clkout_duty_cycle_ fx duty cycle precision for the clkfx and clkfx180 outputs, including the bufgmux and clock tree duty-cycle distortion maximum = [1% of clkfx period + 350] ps clkout_duty_cycle_ fxdv duty cycle precision for the clkfxdv outputs, including the bufgmux and clock tree duty-cycle distortion maximum = [1% of clkfx period + 350] ps lock time lock_fx (2) the time from deassertion at the dcm?s reset input to the rising transition at its locked output. the dfs asserts locked when the clkfx, clkfx180, and clkfxdv signals are valid. lock time requires clkfx_divide < f in /(0.50 mhz) when: 5mhz50mhz ?5?5?5?5ms
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 55 spread spectrum f clkin_fixed_spread_ spectrum frequency of the clkin input for fixed spread spectrum (spread_spectrum = center_low_spread/ center_high_spread) 30 200 30 200 30 200 30 200 mhz t center_low_spread (6) spread at the clkfx output for fixed spread spectrum (spread_spectrum = center_low_spread) maximum = 250 ps t center_high_spread (6) spread at the clkfx output for fixed spread spectrum (spread_spectrum= center_high_spread) maximum = 400 ps f mod_fixed_spread_ spectrum (6) average modulation frequency when using fixed spread spectrum (spread_spectrum = center_low_spread / center_high_spread) ty p i c a l = f in /1024 mhz notes: 1. the values in this table are based on the operating conditions described in ta b l e 2 and ta b l e 5 3 . 2. for optimal jitter tolerance and a faster lock time, use the clkin_period attribute. 3. output jitter is characterized with no input jitter. output jitter strongly depends on the en vironment, including the number of ssos, the output drive strength, clb utilization, clb switching activities, switching frequenc y, power supply, and pcb design. the actual maximum outp ut jitter depends on the system application. 4. the clkfx, clkfxdv, and clkfx180 outputs have a duty cycle of approximately 50%. 5. some duty-cycle and alignment specificati ons include a percentage of the clkfx output period. for example, this data sheet sp ecifies a maximum clkfx jitter of (1% of clkfx period + 200 ps). assuming that the clkfx output frequency is 100 mhz, the equivalent clkfx period is 10 ns, and 1% of 10 ns is 0.1 ns or 100 ps. accordingly, the maximum jitter is (100 ps + 200 ps) = 300 ps. 6. when using center_low_spread, center_high_spread, the valid val ues for clkfx_multiply are limited to 2 through 32, and the va lid values for clkfx_divide are limited to 1 through 4. ta bl e 5 6 : recommended operating conditions for the phase-shif t clock in variable phase mode (dcm_sp) or dynamic frequency synthesis (dcm_clkgen) symbol description speed grade units -3 -3n -2 -1l min max min max min max min max operating frequency ranges psclk_freq frequency for the psclk input. 1 167 1 167 1 167 1 100 mhz input pulse requirements psclk_pulse psclk pulse width as a percentage of the psclk period. 40 60 40 60 40 60 40 60 % ta bl e 5 5 : switching characteristics for the digital frequency synthesizer dfs (dcm_clkgen) (1) (cont?d) symbol description speed grade units -3 -3n -2 -1l min max min max min max min max typical 100 clkfx_divide ------------------------------------------ = typical 240 clkfx_divide ------------------------------------------ =
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 56 ta bl e 5 7 : switching characteristics for the phase-shift clock in variable phase mode (1) symbol description amount of phase shift units phase shifting range max_steps (2) when clkin < 60 mhz, the maximum allowed number of dcm_delay_step steps for a given clkin clock period, where t = clkin clock period in ns. when using clkin_divide_by_2 = true, double the clock-effective clock period. (integer(10 x (tclkin ? 3 ns))) steps when clkin ? 60 mhz, the maximum allowed number of dcm_delay_step steps for a given clkin clock period, where t = clkin clock period in ns. when using clkin_divide_by_2 = true, double the clock-effective clock period. (integer(15 x (tclkin ? 3 ns))) steps fine_shift_range_min minimum guaranteed delay for variable phase shifting. (max_steps x dcm_delay_step_min) ps fine_shift_range_max maximum guaranteed delay for variable phase shifting (max_steps x dcm_delay_step_max) ps notes: 1. the values in this table are based on the operating conditions described in ta b l e 5 1 and ta b l e 5 6 . 2. the maximum variable phase shift range, max_steps, is only va lid when the dcm has no initial fixed-phase shifting, that is, t he phase_shift attribute is set to 0. 3. the dcm_delay_step values are provided at the end of ta bl e 5 2 . ta bl e 5 8 : miscellaneous dcm timing parameters (1) symbol description min max units dcm_rst_pw_min minimum duration of a rst pulse width 3 ? clkin cycles notes: 1. this limit only applies to applications that use the dcm dll out puts (clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv ). the dcm dfs outputs (clkfx, clkfxdv, clkfx180) are unaffected. ta bl e 5 9 : frequency synthesis attribute min max clkfx_multiply (dcm_sp) 2 32 clkfx_divide (dcm_sp) 1 32 clkdv_divide (dcm_sp) 1.5 16 clkfx_multiply (dcm_clkgen) 2 256 clkfx_divide (dcm_clkgen) 1 256 clkfxdv_divide (dcm_clkgen) 2 32 ta bl e 6 0 : dcm switching characteristics symbol description speed grade units -3 -3n -2 -1l t dmcck_psen / t dmckc_psen psen setup/hold 1.50 0.00 1.50 0.00 1.50 0.00 1.50 0.00 ns t dmcck_psincdec / t dmckc_psincdec psincdec setup/hold 1.50 0.00 1.50 0.00 1.50 0.00 1.50 0.00 ns t dmcko_psdone clock to out of psdone 1.50 1.50 1.50 1.50 ns
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 57 spartan-6 device pin-to-pin output parameter guidelines all devices are 100% functionally tested. the representative values for typical pin locations and normal clock loading are listed in ta bl e 6 1 through ta bl e 6 7 . values are expressed in nanos econds unless otherwise noted. ta bl e 6 1 : global clock input to output delay without dcm or pll symbol descrip tion device speed grade units -3 -3n -2 -1l lvcmos25 global clock input to output delay us ing output flip-flop, 12ma, fast slew rate, without dcm or pll t ickof global clock and outff without dcm or pll xc6slx4 6.12 n/a 7.68 9.41 ns xc6slx9 6.12 6.51 7.68 9.41 ns xc6slx16 5.98 6.42 7.48 9.10 ns xc6slx25 6.20 6.69 7.84 9.44 ns xc6slx25t 6.20 6.69 7.84 n/a ns xc6slx45 6.37 6.88 8.10 9.61 ns xc6slx45t 6.37 6.88 8.10 n/a ns xc6slx75 6.39 6.99 8.16 10.08 ns xc6slx75t 6.39 6.99 8.16 n/a ns xc6slx100 6.59 7.18 8.41 10.31 ns xc6slx100t 6.59 7.18 8.41 n/a ns xc6slx150 6.98 7.68 8.80 10.62 ns xc6slx150t 6.98 7.68 8.80 n/a ns notes: 1. listed above are representative values wher e one global clock input drives one vertic al clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 58 ta bl e 6 2 : global clock input to output delay with dcm in system-synchronous mode symbol description device speed grade units -3 -3n -2 -1l lvcmos25 global clock input to output delay us ing output flip-flop, 12ma, fast slew rate, with dcm in system-synchronous mode. t ickofdcm global clock and outff with dcm xc6slx4 4.23 n/a 6.11 6.60 ns xc6slx9 4.235.176.116.60ns xc6slx16 4.28 4.57 5.34 6.36 ns xc6slx25 3.95 4.18 4.59 6.91 ns xc6slx25t 3.95 4.18 4.59 n/a ns xc6slx45 4.37 4.70 5.50 6.85 ns xc6slx45t 4.37 4.70 5.50 n/a ns xc6slx75 3.90 4.23 4.77 6.31 ns xc6slx75t 3.90 4.23 4.77 n/a ns xc6slx100 3.864.164.667.25ns xc6slx100t 3.90 4.16 4.66 n/a ns xc6slx150 4.034.334.836.63ns xc6slx150t 4.03 4.33 4.83 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. dcm output jitter is already in cluded in the timing calculation.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 59 ta bl e 6 3 : global clock input to output delay with dcm in source-synchronous mode symbol description device speed grade units -3 -3n -2 -1l lvcmos25 global clock input to output delay using output flip-flop, 12ma, fast slew rate, with dcm in source-synchronous mode. t ickofdcm_0 global clock and outff with dcm xc6slx4 5.03 n/a 7.21 8.05 ns xc6slx9 5.03 6.13 7.21 8.05 ns xc6slx16 5.08 5.51 6.44 7.96 ns xc6slx25 4.81 5.13 5.69 7.94 ns xc6slx25t 4.81 5.13 5.69 n/a ns xc6slx45 5.26 5.69 6.63 7.92 ns xc6slx45t 5.26 5.69 6.63 n/a ns xc6slx75 4.77 5.18 5.88 7.95 ns xc6slx75t 4.77 5.18 5.88 n/a ns xc6slx100 4.72 5.11 5.76 8.59 ns xc6slx100t 4.76 5.11 5.76 n/a ns xc6slx150 4.90 5.30 5.93 7.93 ns xc6slx150t 4.90 5.30 5.93 n/a ns notes: 1. listed above are representative values w here one global clock input drives one vertic al clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. dcm output jitter is already in cluded in the timing calculation. ta bl e 6 4 : global clock input to output delay with pll in system-synchronous mode symbol description device speed grade units -3 -3n -2 -1l lvcmos25 global clock input to output delay us ing output flip-flop, 12ma, fast slew rate, with pll in system-synchronous mode. t ickofpll global clock and outff with pll xc6slx4 4.57 n/a 6.25 7.34 ns xc6slx9 4.57 5.25 6.25 7.34 ns xc6slx16 4.41 4.64 5.39 6.92 ns xc6slx25 4.03 4.32 4.91 7.64 ns xc6slx25t 4.03 4.32 4.91 n/a ns xc6slx45 4.63 4.96 5.75 7.36 ns xc6slx45t 4.63 4.96 5.75 n/a ns xc6slx75 4.01 4.30 4.88 7.15 ns xc6slx75t 4.01 4.30 4.88 n/a ns xc6slx100 4.02 4.33 4.90 7.37 ns xc6slx100t 4.06 4.33 4.90 n/a ns xc6slx150 3.65 3.98 4.58 6.94 ns xc6slx150t 3.65 3.98 4.58 n/a ns notes: 1. listed above are representative values w here one global clock input drives one vertic al clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. pll output jitter is included in the timing calculation.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 60 ta bl e 6 5 : global clock input to output delay with pll in source-synchronous mode symbol description device speed grade units -3 -3n -2 -1l lvcmos25 global clock input to output delay us ing output flip-flop, 12ma, fast slew rate, with pll in source-synchronous mode. t ickofpll_0 global clock and outff with pll xc6slx4 5.49 n/a 7.44 8.55 ns xc6slx9 5.496.297.448.55ns xc6slx16 5.23 5.77 6.79 8.21 ns xc6slx25 5.00 5.35 6.10 8.54 ns xc6slx25t 5.00 5.35 6.10 n/a ns xc6slx45 5.59 6.03 7.02 8.39 ns xc6slx45t 5.59 6.03 7.02 n/a ns xc6slx75 4.96 5.41 6.22 8.32 ns xc6slx75t 4.96 5.41 6.22 n/a ns xc6slx100 4.975.426.219.08ns xc6slx100t 5.01 5.42 6.21 n/a ns xc6slx150 4.595.065.868.13ns xc6slx150t 4.59 5.06 5.86 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. pll output jitter is included in the timing calculation. ta bl e 6 6 : global clock input to output delay with dcm and pll in system-synchronous mode symbol descrip tion device speed grade units -3 -3n -2 -1l lvcmos25 global clock input to output delay using output flip-flop, 12ma, fast slew rate, with dcm in system-synchronous mode and pll in dcm2pll mode. t ickofdcm_pll global clock and outff with dcm and pll xc6slx4 4.78 n/a 6.32 7.09 ns xc6slx9 4.78 5.24 6.32 7.09 ns xc6slx16 4.70 5.12 5.94 6.63 ns xc6slx25 4.70 5.09 5.92 7.30 ns xc6slx25t 4.70 5.09 5.92 n/a ns xc6slx45 4.63 4.98 5.83 7.26 ns xc6slx45t 4.63 4.98 5.83 n/a ns xc6slx75 4.68 5.04 5.88 6.90 ns xc6slx75t 4.68 5.04 5.88 n/a ns xc6slx100 4.72 5.07 5.92 7.77 ns xc6slx100t 4.76 5.07 5.92 n/a ns xc6slx150 4.44 4.73 5.31 6.96 ns xc6slx150t 4.44 4.73 5.31 n/a ns notes: 1. listed above are representative values w here one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. dcm and pll output jitter are alr eady included in the timing calculation.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 61 ta bl e 6 7 : global clock input to output delay with dcm and pll in source-synchronous mode symbol description device speed grade units -3 -3n -2 -1l lvcmos25 global clock input to output delay us ing output flip-flop, 12ma, fast slew rate, with dcm in source-synchronous mode and pll in dcm2pll mode. t ickofdcm0_pll global clock and outff with dcm and pll xc6slx4 5.58 n/a 7.42 8.54 ns xc6slx9 5.586.197.428.54ns xc6slx16 5.50 6.06 7.05 8.24 ns xc6slx25 5.57 6.04 7.02 8.33 ns xc6slx25t 5.57 6.04 7.02 n/a ns xc6slx45 5.53 5.97 6.96 8.32 ns xc6slx45t 5.53 5.97 6.96 n/a ns xc6slx75 5.55 6.00 6.99 8.54 ns xc6slx75t 5.55 6.00 6.99 n/a ns xc6slx100 5.586.037.029.11ns xc6slx100t 5.62 6.03 7.02 n/a ns xc6slx150 5.325.706.418.26ns xc6slx150t 5.32 5.70 6.41 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. dcm and pll output jitter are alr eady included in the timing calculation.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 62 spartan-6 device pin-to-pin input parameter guidelines all devices are 100% functionally tested. the representative values for typical pin locations and normal clock loading are listed in ta bl e 6 8 through ta bl e 7 4 . values are expressed in nanos econds unless otherwise noted. ta bl e 6 8 : global clock setup and hold without dcm or pll symbol descrip tion device speed grade units -3 -3n -2 -1l input setup and hold time relative to global clock input signal for lvcmos25 standard. (1) t psfd / t phfd no delay global clock and iff (2) without dcm or pll xc6slx4 0.10/ 1.56 n/a 0.10/ 1.83 0.07/ 2.54 ns xc6slx9 0.10/ 1.56 0.10/ 1.57 0.10/ 1.84 0.07/ 2.54 ns xc6slx16 0.12/ 1.42 0.12/ 1.48 0.12/ 1.64 0.13/ 2.19 ns xc6slx25 0.18/ 1.64 0.18/ 1.75 0.18/ 1.99 0.11/ 2.57 ns xc6slx25t 0.18/ 1.64 0.18/ 1.75 0.18/ 1.99 n/a ns xc6slx45 ?0.08/ 1.80 ?0.08/ 1.95 ?0.08/ 2.27 ?0.17/ 2.74 ns xc6slx45t ?0.08/ 1.88 ?0.08/ 1.95 ?0.08/ 2.27 n/a ns xc6slx75 0.13/ 1.97 0.13/ 2.06 0.13/ 2.27 ?0.12/ 3.20 ns xc6slx75t 0.13/ 1.81 0.13/ 2.06 0.13/ 2.27 n/a ns xc6slx100 ?0.14/ 2.15 ?0.14/ 2.24 ?0.14/ 2.56 ?0.17/ 3.44 ns xc6slx100t ?0.14/ 2.03 ?0.14/ 2.24 ?0.14/ 2.56 n/a ns xc6slx150 ?0.24/ 2.42 ?0.24/ 2.74 ?0.24/ 2.95 ?0.60/ 3.75 ns xc6slx150t ?0.24/ 2.55 ?0.24/ 2.74 ?0.24/ 2.95 n/a ns notes: 1. setup and hold times are measured over wors t case conditions (process, voltage, temp erature). setup time is measured relative to the global clock input signal using the slowest proc ess, highest temperature, and lowest voltage. ho ld time is measured re lative to the global c lock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 63 ta bl e 6 9 : global clock setup and hold with dcm in system-synchronous mode symbol description device speed grade units -3 -3n -2 -1l input setup and hold time relative to global clock input signal for lvcmos25 standard. (1) t psdcm / t phdcm no delay global clock and iff (2) with dcm in system-synchronous mode xc6slx4 1.54/ 0.06 n/a 1.75/ 0.12 2.84/ 0.27 ns xc6slx9 1.54/ 0.06 1.63/ 0.12 1.75/ 0.12 2.84/ 0.27 ns xc6slx16 1.72/ ?0.18 1.87/ ?0.17 2.13/ ?0.17 2.31/ 0.26 ns xc6slx25 1.70/ ?0.03 1.78/ ?0.02 2.00/ ?0.02 2.88/ 0.20 ns xc6slx25t 1.79/ 0.07 1.79/ 0.08 2.00/ 0.08 n/a ns xc6slx45 1.74/ ?0.03 1.84/ ?0.02 2.02/ ?0.02 2.64/ 0.52 ns xc6slx45t 1.76/ ?0.01 1.84/ 0.00 2.02/ 0.00 n/a ns xc6slx75 1.86/ 0.11 1.98/ 0.12 2.20/ 0.12 2.96/ 0.58 ns xc6slx75t 1.89/ 0.11 1.98/ 0.12 2.20/ 0.12 n/a ns xc6slx100 1.64/ 0.07 1.72/ 0.08 1.97/ 0.08 2.70/ 0.99 ns xc6slx100t 1.69/ 0.09 1.72/ 0.10 1.97/ 0.10 n/a ns xc6slx150 1.53/ 0.39 1.62/ 0.40 1.82/ 0.40 2.75/ 1.00 ns xc6slx150t 1.53/ 0.39 1.62/ 0.40 1.82/ 0.40 n/a ns notes: 1. setup and hold times are measured over worst case conditions (p rocess, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest pr ocess, highest temperature, and lowest voltage. ho ld time is measured relative to the global c lock input signal using the fastest process, lowest temperature, and highes t voltage. these measurements include dcm clk0 jitter. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle dist ortion incurred using various standards.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 64 ta bl e 7 0 : global clock setup and hold with dcm in source-synchronous mode symbol description device speed grade units -3 -3n -2 -1l input setup and hold time relative to global clock input signal for lvcmos25 standard. (1) t psdcm0 / t phdcm0 no delay global clock and iff (2) with dcm in source-synchronous mode xc6slx4 0.71/ 0.65 n/a 0.72/ 1.22 1.58/ 1.18 ns xc6slx9 0.71/ 0.69 0.71/ 1.19 0.72/ 1.36 1.58/ 1.18 ns xc6slx16 0.86/ 0.52 0.92/ 0.57 1.04/ 0.60 1.02/ 1.06 ns xc6slx25 0.84/ 0.58 0.90/ 0.59 1.01/ 0.59 1.58/ 1.07 ns xc6slx25t 0.94/ 0.58 0.94/ 0.59 1.01/ 0.59 n/a ns xc6slx45 0.85/ 0.70 0.90/ 0.76 0.98/ 0.79 1.34/ 1.34 ns xc6slx45t 0.87/ 0.73 0.90/ 0.76 0.98/ 0.79 n/a ns xc6slx75 1.00/ 0.62 1.06/ 0.63 1.15/ 0.63 1.65/ 1.46 ns xc6slx75t 1.03/ 0.71 1.06/ 0.72 1.15/ 0.72 n/a ns xc6slx100 0.81/ 0.68 0.81/ 0.69 0.94/ 0.69 1.42/ 2.07 ns xc6slx100t 0.86/ 0.68 0.86/ 0.69 0.94/ 0.69 n/a ns xc6slx150 0.68/ 0.98 0.69/ 0.99 0.79/ 0.99 1.45/ 1.60 ns xc6slx150t 0.68/ 0.98 0.69/ 0.99 0.79/ 0.99 n/a ns notes: 1. setup and hold times are measured over worst case conditions (p rocess, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, high est temperature, and lowest voltage. hold time is measured relative to the global c lock input signal using the fastest process, lowest temperature, and highes t voltage. these measurements include dcm clk0 jitter. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle dist ortion incurred using various standards.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 65 ta bl e 7 1 : global clock setup and hold with pll in system-synchronous mode symbol description device speed grade units -3 -3n -2 -1l input setup and hold time relative to global clock input signal for lvcmos25 standard. (1) t pspll / t phpll no delay global clock and iff (2) with pll in system-synchronous mode xc6slx4 1.37/ 0.25 n/a 1.52/ 0.41 2.07/ 0.69 ns xc6slx9 1.37/ 0.21 1.48/ 0.21 1.52/ 0.26 2.07/ 0.69 ns xc6slx16 1.33/ ?0.03 1.53/ ?0.02 1.60/ ?0.02 1.57/ 0.48 ns xc6slx25 1.65/ 0.28 1.71/ 0.28 1.91/ 0.28 2.44/ 0.76 ns xc6slx25t 1.70/ 0.28 1.71/ 0.28 1.91/ 0.28 n/a ns xc6slx45 1.55/ 0.18 1.64/ 0.18 1.75/ 0.18 2.02/ 0.90 ns xc6slx45t 1.57/ 0.18 1.64/ 0.18 1.75/ 0.18 n/a ns xc6slx75 1.77/ 0.21 1.89/ 0.21 2.13/ 0.21 2.46/ 0.53 ns xc6slx75t 1.80/ 0.21 1.89/ 0.21 2.13/ 0.21 n/a ns xc6slx100 1.44/ 0.32 1.52/ 0.32 1.70/ 0.32 1.78/ 0.86 ns xc6slx100t 1.51/ 0.32 1.52/ 0.32 1.70/ 0.32 n/a ns xc6slx150 1.39/ 0.49 1.48/ 0.49 1.67/ 0.49 1.94/ 0.94 ns xc6slx150t 1.41/ 0.49 1.48/ 0.49 1.67/ 0.49 n/a ns notes: 1. setup and hold times are measured over worst case conditions (p rocess, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest pr ocess, highest temperature, and lowest voltage. ho ld time is measured relative to the global c lock input signal using the fastest process, lowest temperature, and highest voltage. these measurements include pll clkout0 jitter. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle dist ortion incurred using various standards.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 66 ta bl e 7 2 : global clock setup and hold with pll in source-synchronous mode symbol description device speed grade units -3 -3n -2 -1l input setup and hold time relative to global clock input signal for lvcmos25 standard. (1) t pspll0 / t phpll0 no delay global clock and iff (2) with pll in source-synchronous mode xc6slx4 0.47/ 1.08 n/a 0.47/ 1.60 1.15/ 1.68 ns xc6slx9 0.47/ 1.08 0.47/ 1.35 0.47/ 1.60 1.15/ 1.68 ns xc6slx16 0.37/ 0.75 0.37/ 0.82 0.51/ 0.94 0.57/ 1.31 ns xc6slx25 0.67/ 1.06 0.67/ 1.06 0.69/ 1.06 1.86/ 1.67 ns xc6slx25t 0.69/ 1.06 0.69/ 1.06 0.69/ 1.06 n/a ns xc6slx45 0.57/ 1.05 0.65/ 1.10 0.65/ 1.18 1.02/ 1.65 ns xc6slx45t 0.59/ 1.06 0.65/ 1.10 0.65/ 1.18 n/a ns xc6slx75 0.86/ 1.04 0.87/ 1.04 0.90/ 1.04 1.34/ 1.55 ns xc6slx75t 0.88/ 1.04 0.88/ 1.04 0.90/ 1.04 n/a ns xc6slx100 0.53/ 1.13 0.54/ 1.13 0.55/ 1.13 0.89/ 2.39 ns xc6slx100t 0.61/ 1.13 0.61/ 1.13 0.61/ 1.13 n/a ns xc6slx150 0.50/ 1.31 0.51/ 1.31 0.52/ 1.31 1.02/ 1.72 ns xc6slx150t 0.52/ 1.31 0.52/ 1.31 0.52/ 1.31 n/a ns notes: 1. setup and hold times are measured over worst case conditions (p rocess, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, high est temperature, and lowest voltage. hold time is measured relative to the global c lock input signal using the fastest process, lowest temperature, and highest voltage. these measurements include pll clkout0 jitter. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle dist ortion incurred using various standards.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 67 ta bl e 7 3 : global clock setup and hold with dcm and pll in system-synchronous mode symbol description device speed grade units -3 -3n -2 -1l input setup and hold time relative to global clock input signal for lvcmos25 standard. (1) t psdcmpll / t phdcmpll no delay global clock and iff (2) with dcm in system-synchronous mode and pll in dcm2pll mode. xc6slx4 1.16/ 0.49 n/a 1.39/ 0.49 2.36/ 0.59 ns xc6slx9 1.16/ 0.44 1.37/ 0.44 1.39/ 0.44 2.36/ 0.59 ns xc6slx16 1.44/ ?0.08 1.49/ ?0.04 1.62 ?0.04 2.06/ 0.55 ns xc6slx25 1.52/ 0.42 1.65/ 0.42 1.83 0.42 2.52/ 0.43 ns xc6slx25t 1.69/ 0.42 1.69/ 0.42 1.83 0.42 n/a ns xc6slx45 1.54/ 0.39 1.59/ 0.39 1.75/ 0.39 2.48/ 0.76 ns xc6slx45t 1.57/ 0.39 1.59/ 0.39 1.75/ 0.39 n/a ns xc6slx75 1.72/ 0.41 1.80/ 0.41 1.99/ 0.41 2.60/ 0.75 ns xc6slx75t 1.74/ 0.41 1.80/ 0.41 1.99/ 0.41 n/a ns xc6slx100 1.34/ 0.51 1.46/ 0.51 1.64/ 0.51 2.12/ 0.90 ns xc6slx100t 1.46/ 0.51 1.46/ 0.51 1.64/ 0.51 n/a ns xc6slx150 1.30/ 0.60 1.40/ 0.60 1.55/ 0.60 2.57/ 0.97 ns xc6slx150t 1.35/ 0.60 1.40/ 0.60 1.55/ 0.60 n/a ns notes: 1. setup and hold times are measured over worst case conditions (p rocess, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, high est temperature, and lowest voltage. hold time is measured relative to the global c lock input signal using the fastest process, lowest temperature, and highest voltage. t hese measurements include cmt jitter; dcm clk0 driving pll, pll clkout0 driving bufg. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle dist ortion incurred using various standards.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 68 ta bl e 7 4 : global clock setup and hold with dcm and pll in source-synchronous mode symbol description device speed grade units -3 - 3n - 2-1l example data input set-up and hold times relative to a forwarded clock input pin, (1) using dcm, pll, and global clock buffer. for situations where clock and data inputs conform to different st andards, adjust the setup and hold values accordingly using the v alues shown in iob switching characteristics, page 20 . t psdcmpll_0 / t phdcmpll_0 no delay global clock and iff (2) with dcm in source-synchronous mode and pll in dcm2pll mode. xc6slx4 0.43/ 1.07 n/a 0.43/ 1.43 1.10/ 1.67 ns xc6slx9 0.43/ 1.03 0.45/ 1.14 0.45/ 1.43 1.10/ 1.67 ns xc6slx16 0.74/ 0.93 0.74/ 1.12 0.74/ 1.21 0.77/ 1.35 ns xc6slx25 0.67/ 1.02 0.76/ 1.11 0.84/ 1.18 1.23/ 1.46 ns xc6slx25t 0.84/ 1.02 0.84/ 1.11 0.84/ 1.18 n/a ns xc6slx45 0.65/ 0.99 0.65/ 1.04 0.71/ 1.12 1.18/ 1.58 ns xc6slx45t 0.67/ 1.00 0.67/ 1.04 0.71/ 1.12 n/a ns xc6slx75 0.86/ 1.01 0.88/ 1.06 0.94/ 1.14 1.29 1.67 ns xc6slx75t 0.89/ 1.03 0.89/ 1.06 0.94/ 1.14 n/a ns xc6slx100 0.50/ 1.10 0.56/ 1.10 0.61/ 1.17 0.84/ 2.24 ns xc6slx100t 0.63/ 1.10 0.63/ 1.10 0.63/ 1.17 n/a ns xc6slx150 0.45/ 1.28 0.47/ 1.28 0.52/ 1.28 1.27/ 1.56 ns xc6slx150t 0.50/ 1.28 0.50/ 1.28 0.52/ 1.28 n/a ns notes: 1. setup and hold times are measured over worst case conditions (p rocess, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, high est temperature, and lowest voltage. hold time is measured relative to the global c lock input signal using the fastest process, lowest temperature, and highest voltage. t he timing values were measured using the fine-phase adjustment f eature of the dcm. these measurements include cmt jitter; dcm clk0 driving pll, pll clkout0 driving bufg. package skew is not included in these measurements. 2. iff = input flip-flop
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 69 source-synchronous switching characteristics the parameters in this section provide the necessary values for calculating timing budgets for spartan-6 fpga source-synchronous transmitter and receiver data-valid windows. ta bl e 7 5 : duty cycle distortion and clock-tree skew symbol description device (1) speed grade units -3 -3n -2 -1l t dcd_clk global clock tree du ty cycle distortion (2) xc6slx4 0.20 n/a 0.20 0.35 ns xc6slx9 0.200.200.200.35 ns xc6slx16 0.20 0.20 0.20 0.35 ns xc6slx25 0.20 0.20 0.20 0.35 ns xc6slx25t 0.20 0.20 0.20 n/a ns xc6slx45 0.20 0.20 0.20 0.35 ns xc6slx45t 0.20 0.20 0.20 n/a ns xc6slx75 0.20 0.20 0.20 0.35 ns xc6slx75t 0.20 0.20 0.20 n/a ns xc6slx100 0.20 0.20 0.20 0.35 ns xc6slx100t 0.20 0.20 0.20 n/a ns xc6slx150 0.35 0.35 0.35 0.35 ns xc6slx150t 0.35 0.35 0.35 n/a ns t ckskew global clock tree skew (3) xc6slx4 0.25 n/a 0.25 0.29 ns xc6slx9 0.250.250.250.29 ns xc6slx16 0.15 0.15 0.15 0.22 ns xc6slx25 0.26 0.26 0.26 0.41 ns xc6slx25t 0.26 0.26 0.26 n/a ns xc6slx45 0.20 0.20 0.20 0.28 ns xc6slx45t 0.20 0.20 0.20 n/a ns xc6slx75 0.56 0.56 0.56 0.50 ns xc6slx75t 0.56 0.56 0.56 n/a ns xc6slx100 0.22 0.22 0.22 0.21 ns xc6slx100t 0.22 0.22 0.22 n/a ns xc6slx150 0.48 0.48 0.48 0.35 ns xc6slx150t 0.48 0.48 0.48 n/a ns t dcd_bufio2 i/o clock tree duty cycle distor tion lx family 0.25 0.25 0.25 0.50 ns lxt family 0.25 0.25 0.25 n/a ns
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 70 t bufioskew i/o clock tree skew across one clock region xc6slx4 0.06 n/a 0.06 0.07 ns xc6slx9 0.060.060.060.07 ns xc6slx16 0.06 0.06 0.06 0.07 ns xc6slx25 0.06 0.06 0.06 0.07 ns xc6slx25t 0.06 0.06 0.06 n/a ns xc6slx45 0.06 0.06 0.06 0.07 ns xc6slx45t 0.06 0.06 0.06 n/a ns xc6slx75 0.06 0.06 0.06 0.07 ns xc6slx75t 0.06 0.06 0.06 n/a ns xc6slx100 0.06 0.06 0.06 0.07 ns xc6slx100t 0.06 0.06 0.06 n/a ns xc6slx150 0.06 0.06 0.06 0.07 ns xc6slx150t 0.06 0.06 0.06 n/a ns notes: 1. lxt devices are not available with a -1l speed gr ade. the lx4 is not available in -3n speed grade. 2. these parameters represent the worst-case duty cycle distortion observable at the pins of the device using lvds output buffer s. for cases where other i/o standards are used, ibis can be used to calculate an y additional duty cycle distorti on that might be caused by asymme trical rise/fall times. 3. the t ckskew value represents the worst-case clock-tr ee skew observable between sequential i/o elem ents. significantly less clock-tree skew exists for i/o registers that ar e close to each other and fed by the same or adjacent clock-tree branches. use the xilinx fpga editor and timing analyzer tools to evaluate clock skew s pecific to your application. ta bl e 7 5 : duty cycle distortion and clock-tree skew (cont?d) symbol description device (1) speed grade units -3 -3n -2 -1l
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 71 ta bl e 7 6 : package skew symbol description device package (2) value units t pkgskew package skew (1) xc6slx4 tqg144 n/a ps cpg196 23 ps csg225 58 ps xc6slx9 tqg144 n/a ps cpg196 23 ps csg225 58 ps ft(g)256 88 ps csg324 64 ps xc6slx16 cpg196 19 ps csg225 70 ps ft(g)256 71 ps csg324 54 ps xc6slx25 ft(g)256 90 ps csg324 61 ps fg(g)484 84 ps xc6slx25t csg324 48 ps fg(g)484 112 ps xc6slx45 csg324 70 ps csg484 99 ps fg(g)484 109 ps fg(g)676 138 ps xc6slx45t csg324 75 ps csg484 100 ps fg(g)484 95 ps xc6slx75 csg484 101 ps fg(g)484 107 ps fg(g)676 161 ps xc6slx75t csg484 107 ps fg(g)484 110 ps fg(g)676 134 ps xc6slx100 csg484 95 ps fg(g)484 155 ps fg(g)676 144 ps xc6slx100t csg484 88 ps fg(g)484 111 ps fg(g)676 147 ps fg(g)900 134 ps
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 72 t pkgskew package skew (1) xc6slx150 csg484 84 ps fg(g)484 103 ps fg(g)676 115 ps fg(g)900 121 ps xc6slx150t csg484 83 ps fg(g)484 88 ps fg(g)676 141 ps fg(g)900 120 ps notes: 1. these values represent the worst-case skew between any two se lectio resources in the package: shortest delay to longest delay from pad to ball. 2. some of these devices are available in both pb and pb -free (additional g) packages as standard ordering options. ta bl e 7 7 : sample window symbol descrip tion device (1) speed grade units -3 -3n -2 -1l t samp sampling error at receiver pins (2) all 510 510 530 740 ps t samp_bufio2 sampling error at receiver pins using bufio2 (3) all 430 430 450 590 ps notes: 1. lxt devices are not available with a -1l speed grade. 2. this parameter indicates the total sampling error of spartan-6 fpga ddr input registers, measured across voltage, temperature , and process. the characterization methodology uses the dcm to capture the ddr input registers? edges of operat ion. these measurements include: - clk0 dcm jitter - dcm accuracy (phase offset) - dcm phase shift resolution these measurements do not include package or clock tree skew. 3. this parameter indicates the total sampling error of spartan-6 fpga ddr input registers, measured across voltage, temperature , and process. the characterization methodology uses the bufio2 clock network and io delay2 to capture the ddr input registers? edges of operation. these measurements do not include package or clock tree skew. ta bl e 7 6 : package skew (cont?d) symbol description device package (2) value units
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 73 ta bl e 7 8 : source-synchronous pin-to-pin setup/hold and clock-to-out using bufio2 symbol description device speed grade units -3 -3n -2 -1l data input setup and hold times relative to a forwarded clock input pin using bufio2 t pscs /t phcs iff setup/hold using bufio2 clock xc6slx4 0.57/ 0.94 n/a 0.95/ 1.12 0.27/ 1.56 ns xc6slx9 0.40/ 0.95 0.50/ 0.96 0.60/ 1.12 0.27/ 1.56 ns xc6slx16 0.48/ 0.74 0.55/ 0.75 0.69/ 0.83 1.27/ 1.31 ns xc6slx25 0.28/ 1.02 0.28/ 1.12 0.28/ 1.24 0.15/ 1.78 ns xc6slx25t 0.28/ 1.08 0.28/ 1.12 0.28/ 1.24 n/a ns xc6slx45 0.42/ 1.19 0.44/ 1.29 0.50/ 1.40 0.12/ 1.83 ns xc6slx45t 0.42/ 1.23 0.44/ 1.29 0.50/ 1.40 n/a ns xc6slx75 0.38/ 1.48 0.38/ 1.63 0.38/ 1.84 0.05/ 2.78 ns xc6slx75t 0.38/ 1.53 0.38/ 1.63 0.38/ 1.84 n/a ns xc6slx100 0.06/ 1.48 0.06/ 1.63 0.06/ 1.87 ?0.03/ 2.72 ns xc6slx100t 0.06/ 1.54 0.06/ 1.63 0.06/ 1.87 n/a ns xc6slx150 0.04/ 1.73 0.04/ 1.75 0.04/ 1.98 ?0.08/ 3.07 ns xc6slx150t 0.04/ 1.73 0.04/ 1.75 0.04/ 1.98 n/a ns pin-to-pin clock-to -out using bufio2 t ickofcs off clock-to-out using bufio2 clock xc6slx4 5.51 n/a 6.95 8.45 ns xc6slx9 5.51 5.89 6.95 8.45 ns xc6slx16 5.31 5.70 6.67 8.21 ns xc6slx25 5.53 6.00 7.02 8.72 ns xc6slx25t 5.53 6.00 7.02 n/a ns xc6slx45 5.76 6.18 7.22 8.77 ns xc6slx45t 5.76 6.18 7.22 n/a ns xc6slx75 5.94 6.46 7.57 9.72 ns xc6slx75t 5.94 6.46 7.57 n/a ns xc6slx100 6.09 6.53 7.60 9.66 ns xc6slx100t 6.09 6.53 7.60 n/a ns xc6slx150 6.29 6.69 7.81 9.94 ns xc6slx150t 6.29 6.69 7.81 n/a ns
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 74 revision history the following table shows the revision history for this document. date version description of revisions 06/24/09 1.0 initial xilinx release. 08/26/09 1.1 added v fs to ta b l e 1 and ta bl e 2 . added r fuse to ta b l e 2 . added xc6slx75 and xc6slx75t to v batt and i batt in ta b l e 1 , ta b l e 2 , and ta bl e 4 . corrected the quiescent supply current for the xc6slx4 in ta b l e 5 . updated ta bl e 1 1 . removed dv ppin from figure 2 . removed f pciecore from ta b l e 2 4 and added values to f pcieuser . added more networking applications to ta bl e 2 5 . updated values for t suspendlow_awake , t suspend_enable , and t scp_awake in ta bl e 4 5 . numerous changes to table 46, page 46 including the addition of new values to various specifications, revising the t smckcso description, and changing the units of t por . also, removed dynamic reconfiguration port (drp) for dcm and pll before and after dclk section from ta b l e 4 6 and updated all the notes. in ta b l e 5 0 , added to f inmax , revised f outmax , and removed pll maximum output frequency for bufio2. revised values for dcm_delay_step in ta b l e 5 2 . updated clkin_freq_fx values in ta b l e 5 3 . 01/04/10 1.2 added -4 speed grade to entire document. upda ted speed specification of -4, -3, -2 speed grades to version 1.03. added -1l speed grade numbers per speed specification 1.00. updated t sol in ta b l e 1 . added -1l rows for lvcmos12, lvcmos15, and lvcmos18 in ta bl e 9 . revised much of the detail in gtp transceiver specifications in ta b l e 1 2 through ta b l e 2 3 . added -2 data to ta bl e 2 5 . updated f max in ta bl e 4 3 . updated descriptions for t dnaclkl and t dnaclkh in ta b l e 4 4 and revised values for all parameters. removed t initaddr from ta b l e 4 6 and added new data. updated values in ta b l e 4 7 through ta b l e 6 0 . added ta b l e 4 9 (bufpll) and ta b l e 5 5 (dcm_clkgen). removed t lockmax note from ta bl e 5 0 . updated note 3 in ta b l e 5 1 . in ta bl e 7 6 : removed xc6slx75csg324 and xc6slx75tcsg324; added xc6slx 75fg(g)484 and xc6slx75fg(g)484. 02/22/10 1.3 production release of xc6slx16 -2 speed grade devices. the changes to ta b l e 2 6 and ta b l e 2 7 includes updating this data sheet to the data in ise v11.5 software with speed specification v1.06. updated maximum of v in and v ts and note 2 in ta bl e 1 . in ta b l e 2 , changed v in , added i in and note 5, revised notes 1, 6, and 7, and added note 8 to r fuse . in ta b l e 4 , removed previous note 1 and added data to i rpu , i rpd , and i batt , changed c in , added r dt and r in_term , and added note 2 and 3. updated v cco2 in ta b l e 6 . added ta b l e 7 and ta b l e 8 . removed pci66_3 from ta b l e 9 . updated pci33_3 and i2c in ta b l e 9 . updated the description of ta bl e 1 1 . completely updated ta bl e 2 5 . updated ta bl e 2 8 including adding values for pci33_3. updated v ref value for hstl_iii_18 in ta b l e 3 0 . updates missing v ref values in ta b l e 3 1 . added simultaneously switching outputs, page 28 . removed t gsrq and t rpw from ta bl e 3 4 and ta bl e 3 5 . also removed t doq from ta bl e 3 5 . removed t isdo_do and note 1 from ta bl e 3 6 . removed t oscck_s and combinatorial section from ta b l e 3 7 . in ta bl e 3 8 , removed t ioddo_t and added new tap param eters and note 2. in ta bl e 3 9 , ta b l e 4 0 , and ta bl e 4 1 , made typographical edits and removed notes. removed clock clk section in ta bl e 4 0 . removed clock clk section and t reg_mux and t reg_m31 in ta bl e 4 1 . added block ram f max values to ta bl e 4 2 . updated values and added note 2 to ta b l e 4 4 . added values to ta bl e 4 5 and removed note 1. numerous changes to ta b l e 4 6 . completely updated ta b l e 5 5 . revised data in ta b l e 6 0 . removed note 3 from ta bl e 6 8 . added values to ta b l e 7 6 . added data to ta bl e 7 7 and ta bl e 7 8 . 03/10/10 1.4 production release of xc6slx45 -2 speed grade devices, which includes changes to ta bl e 2 6 and ta b l e 2 7 updating this data sheet to the data in ise v11.5 software with spe ed specification v1.07. fixed r in_term description in ta b l e 4 . added pci66_3 to ta b l e 7 and replaced note 1. corrected note 1 and the v, max for tmds_33 in ta bl e 8 . in ta b l e 1 0 , added note 1 to lvpecl_33 and tmds_33. also updated specifications for tmds_33. updated the gtp transceiver specifications section including adding values to ta b l e 1 6 , ta b l e 1 7 , and ta bl e 2 0 through ta b l e 2 3 . added pci66_3 back into ta bl e 9 , ta b l e 2 8 , ta bl e 3 0 , ta bl e 3 1 , and ta bl e 3 3 . updated note 3 on ta bl e 3 1 . in ta bl e 3 3 , corrected some typographical errors and fixed sso limits for bank1/3 in fg(g)484 package. corrected t osckc_oce in ta b l e 3 7 . in ta b l e 5 5 , updated clkfx_freeze_var and clkfx_freeze_temp_slope and added typical values to t center_low_spread and t center_high_spread . updated and added values to ta b l e 6 1 through ta b l e 7 5 , and ta b l e 7 8 . in ta b l e 7 6 , revised the xc6slx16-csg324 and the xc6slx45-csg484 and fg(g)484 values.
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 75 06/14/10 1.5 in ta b l e 2 , added note 5 and added temperature range to v fs and r fuse . removed speed grade delineation, revised i rpd description, and updated note 2 in ta bl e 4 . added note 2 to ta b l e 7 . added diff_mobile_ddr to ta bl e 8 and ta b l e 1 0 . added note 4 to ta bl e 1 5 . changed minimum dv ppin in ta b l e 1 6 . updated f gtpdrpclk in ta b l e 1 9 . increased maximum t llskew in ta b l e 2 2 . updated descriptions and added data to ta bl e 2 3 . removed note 1 and added new data to the networking applications section in ta b l e 2 5 . updated ta b l e 2 6 and ta bl e 2 7 to the data in ise v12.1 software with speed specification v1.08. in ta b l e 2 8 , added diff_mobile_ddr and updated -4 speed grade data. updated the maximum i/o pairs per bank in ta bl e 3 2 . updated note 2 on ta bl e 3 8 . revised the f max in ta bl e 4 3 . in ta b l e 4 6 , updated description for t smckcso , revised values for t por and added min value, added t bpiicck and t spiicck . also in ta b l e 4 6 , added device dependencies to f smcck and f rbcck . updated and added data to ta bl e 6 1 through ta bl e 7 5 , and ta b l e 7 8 . in ta b l e 7 6 , added data on the xc6slx45-fg(g)676 and revised the xc6slx45t and xc6slx150t values. the following changes to this specificatio n are addressed in the product change notice xcn10024 , mcb performance and jtag revision code for spartan-6 lx16 and lx45 fpgas . in ta b l e 2 , revised the v ccint to add the memory controller block extended performance specifications. in ta b l e 2 5 , changed the standard specificatio ns and added extended performance specifications for the memory controller block a nd note 2. added note 4 and updated values in ta b l e 3 3 . 06/24/10 1.6 production release of xc6slx45t (-2 and -3 speed grades), xc6slx16 and xc6slx45 (-3 speed grade) devices which includes changes to ta b l e 2 6 and ta b l e 2 7 (ise v12.1 software with speed specification v1.08). added the -3n speed grade, which designates spartan-6 devices that do not support mcb functionality (specifications are identical to the -3 speed grade). this includes changes to ta b l e 2 (note 2), ta bl e 2 5 (note 4), and switching characteristics ( ta bl e 2 6 ). updated simultaneously switching outputs discussion. added -3 speed grade values for t ta p and f mincal values in ta b l e 3 8 . in ta b l e 3 9 , updated t rpw (-2 and -3 speed grade) values and f tog (-3 speed grade) values. in ta b l e 4 7 , updated t gio (-2 and -3 speed grade) values. updated -3 values in spread spectrum section of ta bl e 5 5 . 07/16/10 1.7 production release of specific devices listed in ta b l e 2 6 and ta b l e 2 7 using ise v12.2 software with speed specification v1.11. added note 4 advising designers of the pa tch which contains v1.11. also updated the -1l speed spec ification to v1.04. updated nume rous -4 and -1l values. added -4 t ta p values and f mincal to ta b l e 3 8 . revised t cinck /t ckcin in ta b l e 3 9 . in ta b l e 4 0 , revised t shcko . in ta b l e 4 1 , revised t reg . added new -1l values to ta bl e 4 6 . added and updated values in ta b l e 7 6 . 07/26/10 1.8 production release of xc6slx25, xc6slx25 t, xc6slx100 and xc6slx100t in the specific speed grades listed in ta b l e 2 6 and ta bl e 2 7 using ise v12.2 software with speed specification v1.11. added note 7 to ta bl e 2 and moved v fs and r fuse to a new ta bl e 3 . added i hs and note 4 to ta b l e 4 . added note 1 to ta b l e 2 8 . added and updated sso limits per v cco /gnd pairs in ta b l e 3 3 . added note 3 to ta b l e 4 6 . in ta b l e 5 2 , removed -1l specifications for clkout_per_jitt_dv1/2 and revised clkin_clkfb_phase and clkout_phase_dll values. updated note 3 in both ta b l e 5 4 and ta b l e 5 5 . 08/23/10 1.9 updated values for f gtprange1 , f gtprange2 , and f gpllmin in ta bl e 1 8 . revised -3 and -4 values in ta b l e 2 1 . removed the -1l speed grade readback support restriction and note 3 in ta b l e 4 6 . 11/05/10 1.10 production release of xc6slx4 and xc 6slx9 in the specific speed grades listed in ta bl e 2 6 and ta b l e 2 7 using ise v12.3 software with speed specificatio n v1.12 for the -2 speed grade available in the 12.3 speed files patch . added note 3 advising designers of the patch which contains v1.12. in ta b l e 2 , added note 4. in ta b l e 4 , added note 2. in ta b l e 1 0 , added notes 2 and 3. in ta b l e 4 3 , added note 2. in ta bl e 4 6 , updated symbol for t smwcck /t smcckw , changed -1l values for t usercclkh and t usercclkl , and added and revised the modes for f mcck and f smcck . in ta b l e 5 1 , redefined and expanded description for clkin_freq _dll and rewrote note 3. updated title of ta b l e 5 6 . also in ta bl e 7 5 , revised t dcd_clk for xc6slx150 and xc6slx150t. changed description of t psfd / t phfd in ta bl e 6 8 . for the -1l speed grade, updated data sheet to i se 12.3 software with speed specification v1.05 which revised the values in the following tables: ta bl e 2 5 , ta bl e 2 8 , ta b l e 3 4 , ta b l e 3 5 , ta b l e 3 6 , ta bl e 3 9 through ta b l e 4 2 , ta b l e 4 7 through ta b l e 5 4 , ta bl e 6 0 through ta bl e 7 5 , ta bl e 7 7 , and ta bl e 7 8 . updated notice of disclaimer . date version description of revisions
spartan-6 fpga data sheet: dc and switching characteristics ds162 (v2.0) march 31, 2011 www.xilinx.com preliminary product specification 76 notice of disclaimer the information disclosed to you hereunder (the "materials") is provided solely for the selection and use of xilinx products. t o the maximum extent permitted by applicable law: (1) materials are m ade available "as is" and with all faults, xilinx hereby disclai ms all warranties and conditions, express, implied, or stat utory, including but not limited to warranties of merchantability, non-infringement, or fitness for any pa rticular purpose; and (2) xilinx shall not be liable (whether in contract or tort, including negligence, or under an y other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the materials (includi ng your use of the materials), including for any direct, indire ct, special, incidental, or consequential loss or damage (including loss of da ta, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or xilinx had been advised of the p ossibility of the same. xilinx assumes no obligation to correct any errors contained in the materials, or to advise you of any corrections or update. you may not reproduce, modify, distribute, or publicly display the materials without prior writt en consent. certain products ar e subject to the terms and conditions of the limited warranties which can be viewed at h ttp://www.xilinx.com/warranty.htm ; ip cores may be subject to warranty and support terms contained in a license issued to you by xilinx. xilinx products are not designed or intended to be f ail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of xilinx products in cr itical applications: h ttp://www.xilinx.com/warranty.htm#critapps . automotive applications disclaimer xilinx products are not designed or intended to be fail -safe, or for use in any application requiring fail- safe performance, such as applications related to: (i) the deployment of airbags, (ii) control of a vehicle, unless there is a fail-safe or redundancy fe ature (which does not incl ude use of software in the xilinx device to implement the redundancy) and a wa rning signal upon failure to the operator, or (iii) uses that could lead to death or personal injury. customer assumes the sole risk and liability of any use of xilinx products in such applications. 01/10/11 1.11 production release of xc6slx4 and xc 6slx9 in the specific speed grades listed in ta bl e 2 6 and ta b l e 2 7 using ise v12.4 software with speed specificat ion v1.15 for the -4, -3, -3n, and -2 speed grades. added note 3 to ta bl e 2 7 . also updated the -1l speed grade requirements to ise v12.4 software with speed specification v1.06. re vised -3n definition throughout the document. added note 4 to ta bl e 2 and updated note 5. added information on v ccint to note 1 in ta b l e 5 . updated networking applications -3 values in ta bl e 2 5 to match improvements made in ise v12.4. in ta b l e 2 8 , added note 1 and revised the t iotp values for lvds_33, lvds_25, mini_lvds_33, mini_lvds_25, rsds_33, rsds_25, tmds_33. ppds_33, and ppds_25. added note 3 to ta b l e 5 3 . 02/11/11 1.12 as described in xcn11008 : product discontinuation notice for spartan-6 lxt -4 devices , the -4 speed specifications have been disco ntinued. as outlined in page 2 of the xcn, designers currently using -4 speed specifications should rerun timing analys is using the new -3 speed specifications before moving to a replacement device. updated the networking applications section of ta b l e 2 5 . updated -2 speed spec ifications throughout document and added note 3 to ta b l e 2 7 advising designers to use the -2 speed specification update (v1.17) with the ise 12.4 so ftware patch. added f clkdiv to ta b l e 3 6 and ta b l e 3 7 . updated note 2 in ta b l e 3 8 . updated units for t smckcso and t bpicco in ta b l e 4 6 . updated -1l in ta bl e 6 8 . removed note 2: package delay information is available for these device/package combinations. this information can be used to deskew the package from ta b l e 7 6 . 03/31/11 2.0 production release of xc6slx45 in the specific speed grades listed in ta b l e 2 6 and ta b l e 2 7 using ise v13.1 software with -1l speed specification v1.06. in ta bl e 3 8 , removed values in the -1l column and added note 3 as iodelay2 only supports tap0 for lower-power devices. updated copyright page 1 and notice of disclaimer . date version description of revisions

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